Datasheet
3
Exposed
Thermal Pad
9
10
11
12
8
765
4
2
1
16 15 14 13
PVIN
PVIN
AVIN
SS/TR
SW
SW
SW
PG
PGND
PGND
VOS
EN
FB
AGND
FSW
DEF
TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
SLVSAL5B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
DEVICE INFORMATION
RGT PACKAGE
(TOP VIEW)
Terminal Functions
PIN
(1)
I/O DESCRIPTION
NAME NO.
SW 1,2,3 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG 4 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor; goes high impedance, when device is switched off)
FB 5 I Voltage feedback of adjustable version connect resistive voltage divider to this pin. Its recommended to
connect FB to AGND on fixed output voltage versions for improved thermal performance.
AGND 6 Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
FSW 7 I Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz
(2)
for typical operation)
(3)
DEF 8 I Output Voltage Scaling (Low = nominal, High = nominal + 5%)
(3)
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise
SS/TR 9 I
time. It can be used for tracking and sequencing.
AVIN 10 I Supply voltage for control circuitry. Connect to same source as PVIN.
PVIN 11,12 I Supply voltage for power stage. Connect to same source as AVIN.
EN 13 I Enable input (High = enabled, Low = disabled)
(3)
VOS 14 I Output voltage sense pin and connection for the control loop circuitry.
PGND 15,16 Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Exposed Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane
(4)
. Must be connected
Thermal Pad to AGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability.
(1) For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.
(2) Connect FSW to VOUT or PG in this case.
(3) An internal pull-down resistor keeps logic level low, if pin is floating.
(4) See Figure 39.
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