Datasheet

TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
www.ti.com SLVSAG7B –NOVEMBER 2011–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS
over free-air temperature range (T
A
=-40°C to +85°C), typical values at V
IN
=12V and T
A
=25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
V
IN
Input voltage range
(1)
3 17 V
I
Q
Operating quiescent current EN=High, I
OUT
=0mA, device not switching 17 25 µA
I
SD
Shutdown current
(2)
EN=Low 1.5 4 µA
V
UVLO
Falling Input Voltage 2.6 2.7 2.8 V
Undervoltage lockout threshold
Hysteresis 200 mV
T
SD
Thermal shutdown temperature 160
°C
Thermal shutdown hysteresis 20
CONTROL (EN, DEF, FSW, SS/TR, PG)
High level input threshold voltage (EN,
V
H
0.9 V
DEF, FSW)
V
L
Low level input threshold voltage (EN,
0.3 V
DEF, FSW)
I
LKG
Input leakage current (EN, DEF, FSW) EN=V
IN
or GND; DEF, FSW=V
OUT
or GND 0.01 1 µA
Rising (%V
OUT
) 92 95 98
V
TH_PG
Power good threshold voltage %
Falling (%V
OUT
) 87 90 94
V
OL_PG
Power good output low I
PG
=–2mA 0.07 0.3 V
I
LKG_PG
Input leakage current (PG) V
PG
=1.8V 1 400 nA
I
SS/TR
SS/TR pin source current 2.3 2.5 2.7 µA
POWER SWITCH
V
IN
≥6V 90 170
High-side MOSFET ON-resistance mΩ
V
IN
=3V 120
R
DS(ON)
V
IN
≥6V 40 70
Low-side MOSFET ON-resistance mΩ
V
IN
=3V 50
I
LIMF
High-side MOSFET forward current limit
(3)
V
IN
=12V, T
A
= 25°C 3.6 4.2 4.9 A
OUTPUT
VREF Internal reference voltage
(4)
0.8 V
I
LKG_FB
Input leakage current (FB) TPS62130, V
FB
=0.8V 1 100 nA
Output voltage range (TPS62130) V
IN
≥ V
OUT
0.9 6.0 V
DEF (Output voltage programming) DEF=0 (GND) VOUT
DEF=1 (V
OUT
) VOUT+5%
PWM mode operation, V
IN
≥ V
OUT
+1V –1.8 1.8
PWM mode operation, V
IN
≥ V
OUT
+1V,
V
OUT
Initial output voltage accuracy
(5)
–1.5 1.6 %
T
A
= –10°C to 85°C
Power Save Mode operation, C
OUT
=22µF –2.3 2.8
Load regulation
(6)
V
IN
=12V, V
OUT
=3.3V, PWM mode operation 0.05 %/A
3V ≤ V
IN
≤ 17V, V
OUT
=3.3V, I
OUT
= 1A, PWM 0.02 %/V
Line regulation
(6)
mode operation
(1) The device is still functional down to Under Voltage Lockout (see parameter V
UVLO
).
(2) Current into AVIN+PVIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short
Circuit Protection section).
(4) This is the voltage regulated at the FB pin.
(5) This is the accuracy provided by the device itself (line and load regulation effects are not included). For the fixed voltage versions the
(internal) resistive divider is included.
(6) Line and load regulation depend on external component selection and layout (see Figure 17 and Figure 18).
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