Datasheet
( )
ns
L
VV
II
OUTIN
LIMFtyppeak
30
)(
×
-
+=
PD
L
LIMFtyppeak
t
L
V
II ×+=
)(
TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
www.ti.com
SLVSAG7B –NOVEMBER 2011–REVISED JUNE 2013
(4)
where
I
LIMF
is the static current limit, specified in the ELECTRICAL CHARACTERISTICS,
L is the inductor value,
V
L
is the voltage across the inductor (V
IN
- V
OUT
) and
t
PD
is the internal propagation delay.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch peak current can be calculated as follows:
(5)
Power Good (PG)
The TPS6213X has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and
maintain its specified logic low level. With TPS62130 it is high impedance when the device is turned off due to
EN, UVLO or thermal shutdown. TPS62130A features PG=Low in this case and can be used to actively
discharge Vout (see Figure 51). VIN must remain present for the PG pin to stay Low.
Pin-Selectable Output Voltage (DEF)
The output voltage of the TPS6213X devices can be increased by 5% above the nominal voltage by setting the
DEF pin to High
(1)
. When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal
voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed
information on voltage margining using TPS6213X can be found in SLVA489. A pull down resistor of about
400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating
after initially set to Low. The resistor is disconnected if the pin is set High.
Frequency Selection (FSW)
To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by
connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally
connected to the pin, acting the same way as at the DEF Pin (see above).
Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV.
Thermal Shutdown
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
(1) Maximum allowed voltage is 7V. Therefore it's recommended to connect it to VOUT or PG, not VIN.
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Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133