Datasheet

R1
R2
Approximate circuit area
= 51mm (0.079in )
2 2
R
EN1
R
EN2
R
EN_hys
V
IN
GND
L
C
IN
C
OUT
U1
PG
V
OUT
GND
TPS62125
SLVSAQ5C –MARCH 2012–REVISED DECEMBER 2013 www.ti.com
Table 5. List of Capacitor
CAPACITANCE SIZE CAPACITOR TYPE USAGE SUPPLIER
[µF]
10 0805 GRM21B 25V X5R C
IN
/C
OUT
Murata
10 0805 GRM21B 16V X5R C
OUT
Murata
22 1206 GRM31CR61 16V X5R C
OUT
Murata
22 B2 (3.5x2.8x1.9) 20TQC22MYFB C
IN
/ input Sanyo
protection
.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show frequency variations, poor line and/or load regulation,
stability issues as well as EMI problems. It is critical to provide a low inductance, low impedance ground path.
Therefore, use wide and short traces for the paths conducting AC current of the DC/DC converter. The area of
the AC current loop (input capacitor - TPS62125 - inductor - output capacitor) should be routed as small as
possible to avoid magnetic field radiation. Therefore the input capacitor should be placed as close as possible to
the IC pins as well as the inductor and output capacitor. Use a common Power GND node and a different node
for the signal GND to minimize the effects of ground noise. Keep the common path to the GND pin, which returns
both the small signal components and the high current of the output capacitors as short as possible to avoid
ground noise. A well proven practice is to merge small signal GND and power GND path at the exposed thermal
pad. The FB divider network and the FB line should be routed away from the inductor and the SW node to avoid
noise coupling. The VOS line should be connected as short as possible to the output, ideally to the VOUT
terminal of the inductor. Keep the area of the loop VOS node - inductor - SW node small. The Exposed Thermal
Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation.
Figure 56. EVM board Layout
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