Datasheet

)(
maxminIm LDSONOUTOUTin
RRIVV +´+=
MHz
s
f
SW
1
1
1
max
=»
m
TPS62125
www.ti.com SLVSAQ5C –MARCH 2012–REVISED DECEMBER 2013
The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately ½
I
LPFMpeak
.
With:
T
ON
: high-side MOSFET switch on time [µs]
V
IN
: Input voltage [V]
V
OUT
: Output voltage [V]
L : Inductance [µH]
I
LPFMpeak
: PFM inductor peak current [mA]
The maximum switching frequency can be estimated by:
(3)
100% DUTY CYCLE LOW DROPOUT OPERATION
The device increases the On Time of the high-side MOSFET switch as the input voltage comes close to the
output voltage in order to keep the output voltage in regulation. This reduces the switching frequency.
With further decreasing input voltage VIN, the high-side MOSFET switch is turned on completely. In this case,
the converter provides a low input-to-output voltage difference. This is particularly useful in applications with a
widely variable supply voltage to achieve longest operation time by taking full advantage of the whole supply
voltage span.
The minimum input voltage to maintain output voltage regulation depends on the load current and output voltage,
and can be calculated as:
(4)
With:
I
OUT
= output current
R
DS(ON)max
= maximum high side switch R
DS(ON)
.
R
L
= DC resistance of the inductor
V
OUTmin
= minimum output voltage the load can accept
UNDER-VOLTAGE LOCKOUT
In addition to the EN Comparator, the device includes an under-voltage lockout circuit which prevents the device
from misoperation at low input voltages. Both circuits are fed to an AND gate and prevents the converter from
turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions. The UVLO threshold
is set to 2.9V typical for rising V
IN
and 2.8V typical for falling V
IN
. The hysteresis between rising and falling UVLO
threshold ensures proper start up. Fully functional operation is permitted for an input voltage down to the falling
UVLO threshold level. The converter starts operation again once the input voltage trips the rising UVLO threshold
level and the voltage at the EN pin trips V
TH_EN_ON
.
SOFT START
The TPS62125 has an internal soft-start circuit which controls the ramp up of the output voltage and limits the
inrush current during start-up. This limits input voltage drop.
The soft-start system generates a monotonic ramp up of the output voltage and reaches an output voltage of
1.8V typ. within 240µs after the EN pin was pulled high. For higher output voltages, the ramp up time of the
output voltage can be estimated with a ramp up slew rate of about 12mV/us. TPS62125 is able to start into a pre
biased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its
nominal value. In case the output voltage is higher than the nominal value, the device starts switching once the
output has been discharged by an external load or leakage current to its nominal output voltage value.
During start up the device can provide an output current of half of the high-side MOSFET switch current limit
I
LIMF
. Large output capacitors and high load currents may exceed the current capability of the device during start
up. In this case the start up ramp of the output voltage will be slower.
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