Datasheet

TPS62110, TPS62111

TPS62112, TPS62113

SLVS585C –JULY 2005–REVISED OCTOBER 2012

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FEEDFORWARD-CAPACITOR SELECTION

The feedforward capacitor (C

) is needed to compensate for parasitic capacitance from the feedback pin to GND.

Typically, a value of 4.7 pF to 22 pF is needed for an output voltage divider with a equivalent resistance (R1 in

parallel with R2) in the 150-kΩ range. The value can be chosen based on best transient performance and lowest

output-voltage ripple in PFM mode.

RECOMMENDED CAPACITORS

It is recommended that only X5R or X7R ceramic capacitors be used as input/output capacitors. Ceramic

capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied

across a ceramic capacitor, as on the output and input capacitor of a dc/dc converter. The effect may lead to a

significant capacitance drop, especially for high input/output voltages and small capacitor packages. See the

manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose

a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. The

capacitors listed in Table 3 have been tested with the TPS6211x with good performance.

Table 3. List of Capacitors

MANUFACTURER PART NUMBER SIZE VOLTAGE CAPACITANCE TYPE

TMK316BJ106KL 1206 25 V 10 µF

Taiyo Yuden Ceramic

EMK325BJ226KM 1210 16 V 22 µF

C3225X5R1E106M 25 V 10 µF

1210

TDK C3225X7R1C226M 16 V 22 µF Ceramic

C3216X5R1E106MT 1206 25 V 10 µF

Layout Consideration

A proper layout is critical for the operation of a switched mode power supply, even more at high switching

frequencies. Therefore, the PCB layout of the TPS6211x demands careful attention to ensure operation and to

get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability

and accuracy weaknesses, increased EMI radiation and noise sensitivity.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current should be as short and wide as possible. The input and output capacitance should be placed as close as

possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided.

Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore, keep the SW

node small. Loops which conduct an alternating current should outline an area as small as possible, as this area

is proportional to the energy radiated.

Sensitive nodes like FB and LBI need to be connected with short wires and not nearby high dv/dt signals (that is,

SW). The FB resistors, R1 and R2, and LBI resistors, R5 and R6, should be kept close to the IC and connect

directly to those pins and AGND. The 1-µF capacitor on VINA should connect directly from VINA to AGND.

All Grounds (GND, AGND, and PGND) are directly connected to the Exposed Thermal Pad. The Exposed

Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power

dissipation.

See Figure 20 for the recommended layout of the TPS6211x.

Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113