Datasheet

TPS62110-HT
www.ti.com SLVSAO9B –DECEMBER 2010– REVISED FEBRUARY 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
–55°C to 175°C (PWP) QFP TPS62110HPWP TPS62110HPWP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
V
CC
Supply voltage at VIN, VINA –0.3 V to 20 V
Voltage at SW –0.3 V to V
I
V
I
Voltage at EN, SYNC, LBO, PG –0.3 V to 20 V
Voltage at LBI, FB –0.3 V to 7 V
I
O
Output current at SW 1500 mA
T
J
Maximum junction temperature 190°C
T
stg
Storage temperature –65°C to 175°C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds 300°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS62110
THERMAL METRIC
(1)
PWP UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
32.63
°C/W
ψ
JT
Junction-to-top characterization parameter
(3)
0.848
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
V
CC
Supply voltage at VIN, VINA 3.1 17 V
Maximum voltage at power-good, LBO, EN, SYNC 17 V
Continuous load current
(1)
0.375 A
T
A
Operating temperature –55 175 °C
(1) Higher values of continuous load current may affect long-term reliability of the device at higher operating temperatures. Please refer to
Figure 1 and Figure 2.
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