Datasheet

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   
SLUS446B – MAY 2000 – REVISED DECEMBER 2000
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
f – Frequency – Hz
1 10 100 1 k 10 k 100 k 1 M 10 M 100 M
–50
0
50
100
150
200
Gain
Phase
Phase – Degrees
–50
0
50
100
150
200
Gain – dB
–100
–100
Figure 1. Error Amplifier Gain Phase Response
loop compensation and the TPS6210X series of converters
Feedback-loop compensation in the data sheet examples assumes that the output-filter capacitor is a
mulit-layer ceramic (MLC) type. With this type of output capacitor, the ESR zero will be too high in frequency
to use as part of the compensation network. This can complicate the loop compensation, especially in the
higher-switching frequency versions where error-amplifier bandwidth must be taken into consideration. A
typical PWM- and output-filter response plot is shown in Figure 2. Note the lightly-loaded circuit has a pair of
complex poles that cause the gain peaking and rapid-phase shift near the L-C resonant frequency.
The strategy that has been the best to date for designing a compensator for this circuit has been to use:
an origin pole (no dc path from COMP to FB),
a zero placed below the L-C resonance,
a zero placed above the L-C resonance,
and the remaining pole placed above the last zero.