Datasheet

SLUU070
4
Using the TPS62102 Low-Power High-Efficiency Buck Converter Evaluation Module
3 Feedback Considerations
Figure 2 shows the gain and phase response for the internal error amplifier. In addition to the
compensation configuration used, many other feedback configurations are provided for on the evaluation
module by using the optional component footprints. Figure 3 shows the schematic of the evaluation
module with these additional footprints. As is evident, most any common feedback implementation can be
achieved by simply shorting across pads or inserting passive components. The extra footprints are all
1206 size for ease of use.
UDG–00084
1
3
2
4
8
6
7
5
VIN
SD/SYNC
MODE
GND
SW
PGND
FB
COMP
L1
15
µ
H
C6
10
µ
F
R6
1 k
Ω
C8
100 pF
R1
30.1 k
Ω
C4
1.0 nF
R3 0
Ω
R5
113 k
Ω
R4
35.7 k
Ω
TPS62102
C2
1.0
µ
F
C1
100
µ
F
CB2
CB1
1
2
3
1
2
3
C7{
R2{
C3{ C5{
D1
†
For evaluation use only.
Figure 3. Complete Evaluation Module Schematic
3.1 Error Amplifier
The error amplifier in this chip has a significant impact on what can be done with the feedback loop. To get
a realistic model, assume that the error amplifier has 80 dB (dc) gain, with a 2-MHz GBWP. This may be a
bit conservative, but ensures a stable loop if designed with these constraints.