Datasheet
Table Of Contents
- 1 Features
- 2 Applications
- 3 Description
- 4 Simplified Schematic
- Table of Contents
- 5 Revision History
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameteric Measurement Information
- 9 Detailed Description
- 10 Application and Implementation
- 11 Power Supply Recommendations
- 12 Layout
- 13 Device and Documentation Support
- 14 Mechanical, Packaging, and Orderable Information
SW
SW
DEF
PG
PVIN
PVIN
AVIN
SS
FB
AGND
CP
CN
VOS
PGND
PGND
EN
V
OUT
V
IN
PGND
TPS62090
,
TPS62091
,
TPS62092
,
TPS62093
www.ti.com
SLVSAW2B –MARCH 2012–REVISED APRIL 2014
12 Layout
12.1 Layout Guideline
• It is recommended to place the input capacitor as close as possible to the IC pins PVIN and PGND.
• The VOS connection is noise sensitive and needs to be routed as short and directly to the output pin of the
inductor.
• The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a
single joint connection at the exposed thermal pad of the package.
• This minimizes switch node jitter. The charge pump capacitor connected to CP and CN should be placed
close to the IC to minimize coupling of switching waveforms into other traces and circuits.
• Refer to the evaluation module User Guide (SLVU670) for an example of component placement, routing and
thermal design.
12.2 Layout Example
Figure 30. TPS6209x Layout
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