Datasheet

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1–
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8  C
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Input Capacitor Selection
Layout Considerations
VIN
VIN
EN
MODE
SW
FB
PGND
PGND
SW
GND
2
3
1
4 9
10
5
7
8
6
TPS62020
C3
22 µF
V
I
L1
6.2 µH
C2
22 µF
V
O
The Switch Node Must Be
Kept as Small as Possible
TPS62020
TPS62021
TPS62026
SLVS076C – JUNE 2003 – REVISED DECEMBER 2004
Where the highest output voltage ripple occurs at the highest input voltage, V
I
.
At light load currents, the device operates in power save mode and the output voltage ripple is independent of
the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical
output voltage ripple is 1% of the nominal output voltage.
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The input capacitor should have a minimum value of 10 µF for the TPS6202x. The input capacitor
can be increased without any limit for better input voltage filtering.
Table 2. Input and Output Capacitor Selection
CAPACITOR
CASE SIZE COMPONENT SUPPLIER COMMENTS
VALUE
Taiyo Yuden JMK212BJ106MG Ceramic
10 µF 0805
TDK C12012X5ROJ106K Ceramic
Taiyo Yuden JMK316BJ106KL
10 µF 1206 Ceramic
TDK C3216X5ROJ106M
22 µF 1206 Taiyo Yuden JMK316BJ226ML Ceramic
22 µF 1210 Taiyo Yuden JMK325BJ226MM Ceramic
For all switching power supplies, the layout is an important step in the design especially at high peak currents
and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well
as EMI problems. Therefore, use wide and short traces for the main current paths as indicated in bold in
Figure 16 . These traces should be routed first. The input capacitor should be placed as close as possible to the
IC pins as well as the inductor and output capacitor. The feedback resistor network should be routed away from
the inductor and switch node to minimize noise and magnetic interference. To further minimize noise from
coupling into the feedback network and feedback pin, the ground plane or ground traces should be used for
shielding. A common ground plane or a star ground as shown below should be used. This becomes very
important especially at high switching frequencies of 1.25 MHz.
Figure 16. Layout Diagram
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