Datasheet
SGLS243A − APRIL 2004 − REVISED JUNE 2008
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
EN 8 I Enable. A logic high enables the converter and a logic low forces the device into shutdown mode reducing the supply
current to less than 1 µA.
FB 5 I Feedback pin for the fixed output voltage option. For the adjustable version, an external resistive divider is connected
to FB. The internal voltage divider is disabled for the adjustable version.
FC 2 Supply bypass pin. A 0.1-µF coupling capacitor should be connected as close as possible to this pin for good high
frequency input voltage supply filtering.
GND 3 Ground
ILIM 6 I Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this pin to
V
IN
to set the current limit to typically 1200 mA.
L 9 I/O Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.
PG 4 O Power good comparator output. This is an open-drain output. A pullup resistor should be connected between PG
and V
O
. The output goes active high when the output voltage is greater than 92% of the nominal value.
PGND 10 Power ground. Connect all power grounds to PGND.
SYNC 7 I Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external
clock signal with CMOS level:
SYNC = High: Low-noise mode enabled, fixed frequency PWM operation is forced
SYNC = Low (GND): Power-save mode enabled, PFM/PWM mode enabled.
V
IN
1 I Supply voltage input
NC Not connected
detailed description
operation
The TPS6200x is a step down converter operating in a current mode PFM/PWM scheme with a typical switching
frequency of 750 kHz.
At moderate to heavy loads, the converter operates in the pulse width modulation (PWM) and at light loads the
converter enters a power save mode (pulse frequency modulation) to keep the efficiency high.
In the PWM mode operation, the device operates at a fixed frequency of 750 kHz. At the beginning of each clock
cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via
an internal circuit. The high side switch is turned off when the sensed current causes the PFM/PWM comparator
to trip when the output voltage is in regulation or when the inductor current reaches the current limit (set by ILIM).
After a minimum dead time preventing shoot through current, the low side N-channel MOSFET is turned on and
the current ramps down again. As the clock cycle is completed, the low side switch is turned off and the next
clock cycle starts.
In discontinuous conduction mode (DCM), the inductor current ramps to zero before the end of each clock cycle.
In order to increase the efficiency the load comparator turns off the low side MOSFET before the inductor current
becomes negative. This prevents reverse current flowing from the output capacitor through the inductor and
low side MOSFET to ground that would cause additional losses.
As the load current decreases and the peak inductor current does not reach the power save mode threshold
of typically 120 mA for more than 15 clock cycles, the converter enters a pulse frequency modulation (PFM)
mode.