Datasheet

   
    
     
SGLS243A − APRIL 2004 − REVISED JUNE 2008
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
PFM/PWM
Control Logic
Current Limit
Logic
_
+
Compensation
Soft
Start
Slope Compensation
PFM/PWM
Mode Select
PFM/PWM
Comparator
Error Amplifier
_
+
Current
Sense
Driver
Shoot-Through
Logic
_
+
Undervoltage
Lockout
Bias Supply
10 Ω
_
+
V
ref
= 0.45 V
R2
R1
R1 + R2 ≈ 1 MΩ
Power Good
Sync
+
Oscillator
_
+
Load Comparator
Current Sense
+
Offset
Antiringing
FB
N-Channel
Power MOSFET
P-Channel
Power MOSFET
L
PGND
EN
FB
PG FC (See Note B) V
IN
GND SYNC ILIM
EN
(See
N
ote A)
NOTES: A. The adjustable output voltage version does not use the internal feedback resistor divider. The FB pin is directly connected to the
error amplifier.
B. Do not connect the FC pin to an external power source.