Datasheet
SGLS243A − APRIL 2004 − REVISED JUNE 2008
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
typical application (continued)
V
IN
1
8
6
7
32
9
5
10
4
L1
10 µH
EN
ILIM
SYNC
GND FC
PG
PGND
FB
L
TPS62003
+
C2
47 µF
V
O
= 1.2 V/200 mA
C3
0.1 µF
C1
10 µF
V
I
= 2 V to 3.8 V
L1: Murata LQH4C100K04
C1: 10-µF Ceramic Taiyo Yuden
JMK316BJ106KL
C2: Sanyo 6TPA47M
C3: 0.1-µF Ceramic
Figure 20. Dual Cell NiMH or NiCd to 1.2 V/200 mA − Smallest Solution Size
V
IN
1
8
6
7
32
9
5
10
4
L1
10 µH
EN
ILIM
SYNC
GND FC
PGND
PG
FB
L
TPS62000
+
C2
47 µF
V
O
= 1.1 V or
1.5 V/600 mA
C3
0.1 µF
C1
10 µF
V
I
= 2.5 V to 5.5 V
L1: Sumida CDRH5D28-100
C1: 10-µF Ceramic Taiyo Yuden
JMK316BJ106KL
C2: Sanyo 6TPA47M
C3: 0.1-µF Ceramic
PG
†
R4
820 kΩ
R1
470 kΩ
R2
326 kΩ
C
(ff)
ĕ
150 pF
R3
524 kΩ
Logic Input
Hi V
O
= 1.5 V
Low V
O
= 1.1 V
Q1
BSS138
†
Use a small R-C filter to filter wrong reset signals during output voltage transitions.
‡
A large value is used for C
(ff)
to compensate for the parasitic capacitance introduced into the regulation loop by Q1.
Figure 21. Dynamic Output Voltage Programming As Used in Low Power DSP Applications