Datasheet
SGLS243A − APRIL 2004 − REVISED JUNE 2008
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout considerations
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well
as EMI problems.
Therefore, use wide and short traces for the main current paths as indicted in bold in Figure 16. The input
capacitor should be placed as close as possible to the IC pins, as well as the inductor and output capacitor. Place
the bypass capacitor, C3, as close as possible to the FC pin. The analog ground, GND, and the power ground,
PGND, need to be separated. Use a common-ground node, as shown in Figure 16, to minimize the effects of
ground noise.
V
IN
1
8
6
7
32
9
5
10
4
L1
EN
ILIM
SYNC
GND FC
PG
PGND
FB
L
TPS62000
+
C
o
V
O
C3
C
i
V
I
R3
R1
C
(ff)
R2
+
PG
Figure 16. Layout Diagram
typical application
V
IN
1
8
6
7
32
9
5
10
4
L1
22 µH
EN
ILIM
SYNC
GND FC
PG
PGND
FB
L
TPS62007
C2
10 µF
V
O
= 3.3 V/600 mA
Power
Good
C3
0.1 µF
C1
10 µF
V
I
= 5 V
680 kΩ
L1: Sumdia CDRH5D28-220
C1, C2: 10-µF Ceramic Taiyo Yuden
JMK316BJ106KL
C3: 0.1-µF Ceramic
Figure 17. Standard 5 V to 3.3 V/600 mA Conversion − High Efficiency