Datasheet

t-Time=50 s/divm
I
(500mA/div)
L
V
(500mV/div-4.95VOffset)
OUT
V =3.6V,
IN
V =4.95V
I =1750mA
OUT
LIM
PFM/PWMOperation
ENPSMbit=1
I
(500mA/div)
OUT
50mA to500mA LoadStep
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000 10000
I -OutputCurrent-mA
O
Efficiency-%
V =4.2V
IN
V =3.6V
IN
V =2.5V
IN
V =4.95V
VoltageModeRegulation
OUT
I =1750mA
LIM
V =3V
IN
PFM/PWMOperation
ForcedPWMOperation
www.ti.com BOARD LAYOUT
4.3 Voltage Mode
Figure 8. Efficiency vs Input Voltage Figure 9. Load Transient
5 BOARD LAYOUT
Proper board layout is important for all high-frequency switch-mode power supplies. Figure 10 through
Figure 14 show the board layout for the TPS61310EVM-638 PCB. The nodes with high switching
frequencies and currents are kept as short as possible to minimize trace inductance. Careful attention has
been given to the routing of high-frequency current loops. A single-point grounding scheme is used. Also,
the majority of the heat sinking for this device occurs through the top layer traces and vias pulled from the
IC’s solder bumps that carry high currents. For specific layout guidelines, see the TPS61310 data sheet.
Figure 10. Assembly Layer
7
SLVU419– April 2011 TPS61310EVM-638 Evaluation Module User Guide
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