Datasheet

TPS61260, TPS61261
SLVSA99A –MAY 2011–REVISED FEBRUARY 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE DEVICE OPTIONS
(1)
T
A
OUTPUT VOLTAGE PACKAGE MARKING PACKAGE PART NUMBER
(2)
Adjustable QWD TPS61260DRV
–40°C to 85°C 6-Pin SON
3.3 V QWE TPS61261DRV
(1) Contact the factory to check availability of other fixed output voltage versions.
(2) For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
VIN, L, VOUT, EN, FB –0.3 5.0 V
Voltage range
(2)
RI –0.3 3.6 V
Operating junction, T
J
–40 150 °C
Temperature range
Storage, T
stg
–65 150 °C
Human Body Model - (HBM) 2 kV
ESD rating
(3)
Charge Device Model - (CDM) 0.5 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS61260,
TPS61261
THERMAL METRIC
(1)
UNITS
DRV
6 PINS
θ
JA
Junction-to-ambient thermal resistance 89
θ
JC(top)
Junction-to-case(top) thermal resistance 100
θ
JB
Junction-to-board thermal resistance 35
°C/W
ψ
JT
Junction-to-top characterization parameter 2
ψ
JB
Junction-to-board characterization parameter 36
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance 8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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