Datasheet

L1
C
IN
C
OUT
U1
GND
V
IN
V
OUT
GND
EN
BP
TPS61253, TPS61254, TPS61256
TPS61258, TPS61259
SLVSAG8C –SEPTEMBER 2011–REVISED AUGUST 2012 www.ti.com
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, I
L
• Output ripple voltage, V
OUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. V
OUT
immediately shifts by an amount equal to ΔI
(LOAD)
x ESR, where ESR
is the effective series resistance of C
OUT
. ΔI
(LOAD)
begins to charge or discharge C
OUT
generating a feedback
error signal used by the regulator to return V
OUT
to its steady-state value. The results are most easily interpreted
when the device operates in PWM mode.
During this recovery time, V
OUT
can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET r
DS(on)
) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
LAYOUT CONSIDERATIONS
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to the ground pins of the IC.
Figure 37. Suggested Layout (Top)
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