Datasheet

ESR OUT ESR
V I R= g
( )
OUT OUT IN
MIN
OUT
I V V
C
f V V
-
=
D
g
g g
TPS61253, TPS61254, TPS61256
TPS61258, TPS61259
www.ti.com SLVSAG8C –SEPTEMBER 2011–REVISED AUGUST 2012
OUTPUT CAPACITOR
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly
recommended. This small capacitor should be placed as close as possible to the V
OUT
and GND pins of the IC.
To get an estimate of the recommended minimum output capacitance, Equation 6 can be used.
(6)
Where f is the switching frequency which is 3.5MHz (typ.) and ΔV is the maximum allowed output ripple.
With a chosen ripple voltage of 20mV, a minimum effective capacitance of 9μF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
Equation 7
(7)
An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This
is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V
and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive
at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause
lower output voltage ripple as well as lower output voltage drop during load transients but the total output
capacitance value should not exceed ca. 50µF.
DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the
device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size
and voltage rating in combination with material are responsible for differences between the rated capacitor value
and it's effective capacitance. For instance, a 10µF X5R 6.3V 0603 MLCC capacitor would typically show an
effective capacitance of less than 4µF (under 5V bias condition, high temperature).
In applications featuring high pulsed load currents (e.g. TPS61253 based solution) it is recommended to run the
converter with a reasonable amount of effective output capacitance, for instance x2 10µF X5R 6.3V 0603 MLCC
capacitors connected in parallel.
INPUT CAPACITOR
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible
to the device. While a 4.7μF input capacitor is sufficient for most applications, larger values may be used to
reduce input current ripple without limitations.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between C
I
and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and C
I
.
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