Datasheet

( )
OUT IN DS(on) OUT
V V DCR r I= - + g
TPS61252
www.ti.com SLVSAG3 –SEPTEMBER 2010
POWER-SAVE MODE
The TPS61252 integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold
voltage. During the power save operation when the output voltage is above the set threshold the converter turns
off some of the inner circuits to save energy.
The PFM mode is left and PWM mode entered in case the output current can no longer be supported in PFM
mode.
100% DUTY-CYCLE MODE
If V
IN
> V
OUT
the TPS61251 offers the lowest possible input-to-output voltage difference while still maintaining
current limit operation with the use of the 100% duty-cycle mode. In this mode, the PMOS switch is constantly
turned on. During this operation the output voltage follows the input voltage and will not fall below the
programmed value if the input voltage decreases below V
OUT
. The output voltage drop during 100% mode
depends on the load current and input voltage, and the resulting output voltage is calculated as:
(4)
with:
DCR is the DC resistance of the inductor
r
DS(on)
is the typical on-resistance of the PMOS switch
ENABLE
The device is enabled by setting EN pin to a voltage above 1 V. At first, the internal reference is activated and
the internal analog circuits are settled. Afterwards, the output voltage ramps up controlled by the softstart
circuitry. The output voltage reaches its nominal value as fast as the current limit settings and the load condition
allows it.
The EN input can be used to control power sequencing in a system with several DC/DC converters. The EN pin
can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply
rails. With EN = GND, the device enters shutdown mode.
UNDER-VOLTAGE LOCKOUT (UVLO)
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. It disables the output stage of the converter once the falling V
IN
trips the under-voltage
lockout threshold V
UVLO
which is typically 2.0V. The device starts operation once the rising V
IN
trips V
UVLO
threshold plus its hysteresis of 100 mV at typ. 2.1V.
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