Datasheet

A2 A1
B2
B1
C2 C1
D
E
A1
YMSCC
LLLL
Code:
•
YM- YearMonthdatecode
• S- Assemblysitecode
• CC-ChipCode
• LLLL -Lottracecode
ChipScalePackage
(BottomView)
ChipScalePackage
(TopView)
TPS61240, TPS61241
www.ti.com SLVS806B –APRIL 2009– REVISED FEBRUARY 2012
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow into the system
The maximum recommended junction temperature (T
J
) of the TPS6124x devices is 105°C. The thermal
resistance of the 6-pin CSP package (YFF-6) is R
θJA
= 125°C/W. Regulator operation is specified to a maximum
steady-state ambient temperature T
A
of 85°C. Therefore, the maximum power dissipation is about 160 mW.
P
D(Max)
= [T
J
(max)-T
A
] / θ
JA
= [105°C - 85°C] / 125°C/W = 160mW
CHIP SCALE PACKAGE DIMENSIONS
The TPS6124x device is available in a 6-bump chip scale package (YFF, NanoFree
TM
). The package dimensions
are given as:
D E
Max = 1280 µm Max = 890 µm
Min = 1220 µm Min = 830 µm
Copyright © 2009–2012, Texas Instruments Incorporated 17