Datasheet

³ ´
2
L
C
2
(5)
Layout Considerations
V
IN
V
OUT
GND
L1
C1
C2
R1
R2
GND
Enable
V
IN
V
OU
T
TPS61220
TPS61221
TPS61222
www.ti.com ............................................................................................................................................................................................... SLVS776 – JANUARY 2009
A minimum capacitance value of 4.7 µ F should be used, 10 µ F are recommended. If the inductor value exceeds
4.7 µ H, the value of the output capacitance value needs to be half the inductance value or higher for stability
reasons, see Equation 5 .
The TPS6122x is not sensitive to the ESR in terms of stability. Using low ESR capacitors, such as ceramic
capacitors, is recommended anyway to minimize output voltage ripple. If heavy load changes are expected, the
output capacitor value should be increased to avoid output voltage drops during fast load transients.
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
paths. The input and output capacitor, as well as the inductor should be placed as close as possible to the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids
ground shift problems, which can occur due to superimposition of power ground current and control ground
current. Assure that the ground traces are connected close to the device GND pin.
Figure 26. PCB Layout Suggestion for Adjustable Output Voltage Options
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Product Folder Link(s): TPS61220 TPS61221 TPS61222