Datasheet
C2
1 Fm
10 WLEDinseries, 120 mA total
C5
10 nF
C2a
L1
10 Hm
Q1
D2
D1
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
V
O
SWFault
V
BAT
Cin
EN
DCTRL
ISET
PGND
GND
R1
TPS61181/2
C4
0.1 Fm
Optional
5 Vto 24 V
C1a
EN
PWMDimming
R2
51Ω
C3
1 Fm
C1
2.2 Fm
C1, C1a: MurataGRM219R61E225K
C2, C2a: MurataGRM21BR71H105K
C3: MurataGRM21BR71H105K
C4: MurataGRM185R61A105K
C5: MurataGRM155R71H103K
L1: TOKO A915AY-100M
D1: VISHAY SS2P5-E3/84A
R3
100kW
2.2 Fm
1 Fm
TPS61180/1/2
SLVS801E –DECEMBER 2007–REVISED APRIL 2013
www.ti.com
In addition, connecting a 10-nF/50V ceramic capacitor between the V
O
pin and IFB1 pin can further reduce the
output AC ripple during the PWM dimming. Since this capacitor is subject to large AC ripple, choose a small
package such as 0402 to prevent it from producing noise.
LAYOUT CONSIDERATION
As for all switching power supplies, especially those providing high current and using high switching frequencies,
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C3 in the typical
application circuit, needs not only to be close to the V
BAT
pin, but also to the GND pin in order to reduce the input
ripple seen by the IC. The input capacitor, C1 in the typical application circuit, should be placed close to the
inductor. The SW pin carries high current with fast rising and falling edges. Therefore, the connection between
the pin to the inductor and Schottky should be kept as short and wide as possible. It is also beneficial to have the
ground of the output capacitor C2 close to the PGND pin since there is large ground return current flowing
between them. When laying out signal ground, it is recommended to use short traces separated from power
ground traces, and connect them together at a single point, for example on the thermal pad.
Thermal pad needs to be soldered on to the PCB and connected to the GND pin of the IC. Additional thermal via
can significantly improve power dissipation of the IC.
ADDITIONAL APPLICATION CIRCUITS
Figure 16. Audible Noise Reduction Circuit
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Product Folder Links: TPS61180/1/2