Datasheet

f − Frequency − kHz
Gain − dB
Phase – °
–180
–90
f
Z
f
C
0
90
180
f 2
p
<–
f 1
p
Phase
Gain
Kcomp
TPS61175
www.ti.com SLVS892B –DECEMBER 2008–REVISED FEBRUARY 2012
Figure 17. Bode Plot of Feedback Resistors and Compensated Amplifier Gain and Phase
The next step is to choose the loop crossover frequency, f
C
. The higher in frequency that the loop gain stays
above zero before crossing over, the faster the loop response will be and therefore the lower the output voltage
will droop during a step load. It is generally accepted that the loop gain cross over no higher than the lower of
either 1/5 of the switching frequency, f
SW
, or 1/3 of the RHPZ frequency, f
RHPZ
. To approximate a single pole roll-
off up to f
P2
, select R3 so that the compensation gain, K
COMP
, at f
C
on Figure 17 is the reciprocal of the gain, K
PW
,
read at frequency f
C
from the Figure 16 bode plot or more simply
K
COMP
(f
C
) = 20 × log(G
EA
× R3 × R2/(R2+R1)) = 1/K
PW
(f
C
)
This makes the total loop gain, T(s) = G
PS
(s) × H
EA
(s), zero at the f
C
. Then, select C4 so that f
Z
≅ f
C
/10 and
optional f
P2
> f
C
*10. Following this method should lead to a loop with a phase margin near 45 degrees. Lowering
R3 while keeping f
Z
≅ f
C
/10 increases the phase margin and therefore increases the time it takes for the output
voltage to settle following a step load.
In the TPS61175, if the FB pin voltage changes suddenly due to a load step on the output voltage, the error
amplifier increases its transconductance for 8-ms in an effort to speed up the IC’s transient response and reduce
output voltage droop due to the load step. For example, if the FB voltage decreases 10-mV due to load change,
the error amplifier increases its source current through COMP by 5 times; if FB voltage increases 11-mV, the
sink current through COMP is increased to 3.5 times normal value. This feature often results in saw tooth ringing
on the output voltage, shown as Figure 9. Designing the loop for greater than 45 degrees of phase margin and
greater than 10db gain margin minimizes the amplitude of this ringing. This feature is disabled during soft start.
LAYOUT CONSIDERATIONS
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well
as noise problems. To maximize efficiency, switch rise and fall times are very fast. To prevent radiation of high
frequency noise (eg. EMI), proper layout of the high frequency switching path is essential. Minimize the length
and area of all traces connected to the SW pin and always use a ground plane under the switching regulator to
minimize interplane coupling. The high current path including the switch, Schottky diode, and output capacitor,
contains nanosecond rise and fall times and should be kept as short as possible. The input capacitor needs not
only to be close to the VIN pin, but also to the GND pin in order to reduce the Iinput supply ripple.
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