Datasheet

CTRL
GND
C3
L1
R2
Vin
CTRL
SW
FB
COMP
GND
C1 Vin
C2
Vout
Minimizethe
areaofthis
trace
Placeenough
VIAsaround
thermalpadto
enhancethermal
performance
R3
R1
Note: minimizethetrace
areaatFBpinand
COMP pin
P
D(max)
+
125
°
C * T
A
RqJA
TPS61170-Q1
SLVSAX2 – SEPTEMBER 2011 www.ti.com
Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For
example, larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switching
frequency. So, the effective capacitance is significantly lower. The DC bias can also significantly reduce
capacitance. Ceramic capacitors can lose as much as 50% of its capacitance at its rated voltage. Therefore,
choose a ceramic capacitor with a voltage rating at least 1.5X its expected dc bias voltage.
The capacitor in the range of 1μF to 4.7μF is recommended for input side. The output typically requires a
capacitor in the range of 1μF to 10μF. The output capacitor affects the loop stability of the boost regulator. If the
output capacitor is below the range, the boost regulator can potentially become unstable.
The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)
LAYOUT CONSIDERATIONS
As for all switching power supplies, especially those switching at high frequencies and/or providing high currents,
layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well
as noise problems. To maximize efficiency, switch rise and fall times should be as short as possible. To reduce
radiation of high frequency switching noise and harmonics, proper layout of the high frequency switching path is
essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane
under the switching regulator to minimize interplane coupling. The high current path including the switch,
Schottky diode, and output capacitor, contains nanosecond rise and fall times and should be kept as short as
possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to
reduce the IC supply ripple. Figure 18 shows a sample layout
Figure 18. PCB Layout Recommendation
THERMAL CONSIDERATIONS
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the TPS61170-Q1. Calculate the maximum allowable dissipation,
P
D(max)
, and keep the actual dissipation less than or equal to P
D(max)
. The maximum-power-dissipation limit is
determined using Equation 14:
(14)
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Product Folder Link(s): TPS61170-Q1