Datasheet

CTRL
GND
C3
L1
Rset
Vin
CTRL
SW
FB
COMP
GND
C1 Vin
C2
LEDs IN
LEDs Out
Minimize the
area of this
trace
Place enough
VIAs around
thermal pad to
enhance thermal
performance
P
D(max)
+
125
°
C * T
A
RqJA
TPS61160
TPS61161
SLVS791C –NOVEMBER 2007–REVISED APRIL 2012 www.ti.com
LAYOUT CONSIDERATIONS
As for all switching power supplies, especially those high frequency and high current ones, layout is an important
design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.
To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of
high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the
length and area of all traces connected to the SW pin and always use a ground plane under the switching
regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output
capacitor, contains high current rising and falling in nanosecond and should be kept as short as possible. The
input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the IC
supply ripple. Figure 17 shows a sample layout.
Figure 17. Sample Layout
THERMAL CONSIDERATIONS
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the TPS61160/1. Calculate the maximum allowable dissipation, P
D(max)
,
and keep the actual dissipation less than or equal to P
D(max)
. The maximum-power-dissipation limit is determined
using Equation 8:
(8)
where, T
A
is the maximum ambient temperature for the application. R
θJA
is the thermal resistance junction-to-
ambient given in Power Dissipation Table.
The TPS61160/1 comes in a thermally enhanced QFN package. This package includes a thermal pad that
improves the thermal capabilities of the package. The R
θJA
of the QFN package greatly depends on the PCB
layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using
thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB
Attachment application report (SLUA271).
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