Schematic
3-4
Figure 3−3. Bottom Layer
3.3 Schematic
Figure 3−4. TPS6112x EVM Circuit Diagram
SWN
C1
10 µF
L1
10 µH
R1
R2
VBAT
VOUT
FB
LDOIN
LDOSENSE
LDOOUT
R7 R8
C2
2.2 µF
C3
100 µF
U1
LBO
PGOOD
PGND
LBI
SKIPEN
EN
LDOEN
GND
TPS6112xPW
C5
2.2 µF
R3
R4
R5
R6
LBO
PGOOD
LDOOUT
OUTPUT
ENLDO
EN
SKIPEN
INPUT
R9
R10
SWP
C4
