Datasheet

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PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SWP
SWN
PGND
VBAT
LBI
SKIPEN
EN
LDOEN
VOUT
FB
PGOOD
LBO
GND
LDOSENSE
LDOOUT
LDOIN
PW PACKAGE
(TOP VIEW)
VBAT
LBI
SKIPEN LDOSENSE
PGOOD
PGND
GND
LBO
EN
LDOEN
LDOIN
LDOOUT
SWN SWP VOUT FB
RSA PACKAGE
(TOP VIEW)
TPS61120
TPS61122, TPS61121
SLVS427C – JUNE 2002 – REVISED APRIL 2004
CONTROL STAGE
Power-Good threshold V
O
= 3.3 V 0.9xV
o
0.92xV
o
0.95xV
o
V
Power-Good delay 30 µs
Power-Good output low voltage V
O
= 3.3 V, I
OI
= 100 µA 0.04 0.4 V
Power-Good output low current 100 µA
Power-Good output leakage V
PG
= 7 V 0.01 0.1 µA
current
Over-Temperature protection 140 °C
Over-Temperature hysteresis 20 °C
Terminal Functions
TERMINAL
NO. I/O DESCRIPTION
NAME
PW RSA
EN 7 5 I DC/DC-enable input. (1/VBAT enabled, 0/GND disabled)
FB 15 13 I DC/DC voltage feedback of adjustable versions
GND 12 10 I/O Control/logic ground
LBI 5 3 I Low battery comparator input (comparator enabled with EN)
LBO 13 11 O Low battery comparator output (open drain)
LDOEN 8 6 I LDO-enable input (1/LDOIN enabled, 0/GND disabled)
LDOOUT 10 8 O LDO output
LDOIN 9 7 I LDO input
LDOSENSE 11 9 I LDO feedback for voltage adjustment, must be connected to LDOOUT
at fixed output voltage versions
SWP 1 15 I DC/DC rectifying switch input
PGND 3 1 I/O Power ground
PGOOD 14 12 O DC/DC output power good (1 : good, 0 : failure) (open drain)
SKIPEN 6 4 I Enable/disable power save mode (1: VBAT enabled, 0: GND disabled)
SWN 2 16 I DC/DC switch input
VBAT 4 2 I Supply pin
VOUT 16 14 O DC/DC output
PowerPAD
TM
Must be soldered to achieve appropriate power dissipation. Should be
connected to PGND.
4