Datasheet

www.ti.com
LAYOUT CONSIDERATIONS
APPLICATION EXAMPLES
SWN
C3
10 µF
L1
10 µH
R1
R2
VBAT
VOUT
LDOIN
LDOSENSE
LDOOUT
R7 R9
C6
2.2 µF
C4
100 µF
U1
LBO
PGOOD
PGND
LBI
SKIPEN
EN
LDOEN
GND
TPS61121PW
List of Components:
U1 = TPS61121PW
L1 = Sumida CDRH73–100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
3.3 V,
>250 mA
C5
2.2 µF
1.5 V,
>120 mA
LBO
PGOOD
SWP
TPS61120
TPS61122, TPS61121
SLVS427C – JUNE 2002 – REVISED APRIL 2004
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
Figure 25. Solution for Maximum Output Power
19