Datasheet
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Capacitor Selection
Input Capacitor
Output Capacitor DC/DC Converter
C
min
I
OUT
V
OUT
V
BAT
ƒ V V
OUT
(6)
V
ESR
I
OUT
R
ESR
(7)
Small Signal Stability
A
REG
d
V
FB
A
REG
d5(R3 R4)
R4 (1 i 2.3 s)
(8)
LAYOUT CONSIDERATIONS
TPS61090
TPS61091, TPS61092
SLVS484A – JUNE 2003 – REVISED APRIL 2004
At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in
parallel, placed close to the IC, is recommended.
The major parameter necessary to define the minimum value of the output capacitor is the maximum allowed
output voltage ripple in steady state operation of the converter. This ripple is determined by two parameters of
the capacitor, the capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the
defined ripple, supposing that the ESR is zero, by using equation Equation 6 :
Parameter f is the switching frequency and ∆V is the maximum allowed ripple.
With a chosen ripple voltage of 10 mV, a minimum capacitance of 53 µF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 7 :
An additional ripple of 40 mV is the result of using a tantalum capacitor with a low ESR of 80 mΩ. The total ripple
is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this
example, the total ripple is 50 mV. Additional ripple is caused by load transients. This means that the output
capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor
has to completely supply the load during the charging phase of the inductor. A reasonable value of the output
capacitance depends on the speed of the load transients and the load current during the load change. With the
calculated minimum value of 53 µF and load transient considerations, a reasonable output capacitance value is
in a 100 µF range. For economical reasons this usually is a tantalum capacitor. Because of this the control loop
has been optimized for using output capacitors with an ESR of above 30 mΩ.
When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage
version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the
range of 10 pF in parallel to R3 helps to obtain small signal stability with lowest ESR output capacitors. For more
detailed analysis the small signal transfer function of the error amplifier and regulator, which is given is
Equation 8 , can be used.
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
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