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TPS6105X I2C UPDATE SEQUENCE
Slave Address R/W ACK Register Address ACK Data ACK PS
1
7
1 1 1 1 1
8 8
ACK = Acknowledge
S = START condition
P = STOP condition
FromMasterto TPS6105x
From TPS6105xtoMaster
“0” Write
Slave Address R/W ACK Register Address ACK
Data ACK P
S
1
7
1 1 1 1 1
8
8
ACK = Acknowledge
S = START condition
Sr = REPEATEDSTART condition
P = STOP condition
FromMasterto TPS6105x
From TPS6105xtoMaster
“0” Write
Sr
1
Slave Address R/W
7
1
“1” Read
ACK
1
TPS61050
TPS61052
SLUS525 – MARCH 2007
The TPS6105x requires a start condition, a valid I
2
C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6105x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I
2
C address selects the TPS6105x. TPS6105x performs an
update on the rising edge of the SCL clock that follows the ACK bit transmission.
Figure 46. Write Data Transfer Format in F/S-Mode
Figure 47. Read Data Transfer Format in F/S-Mode
SLAVE ADDRESS BYTE
MSB LSB
X 0 1 1 0 0 1 1
The slave address byte is the first byte received following the START condition from the master device.
REGISTER ADDRESS BYTE
MSB LSB
0 0 0 0 0 0 D1 D0
Following the successful acknowledgement of the slave address, the bus master will send a byte to the
TPS6105x, which will contain the address of the register to be accessed. The TPS6105x contains four 8-bit
registers accessible via a bidirectional I2C-bus interface. All internal registers have read and write access.
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