Datasheet

TPS61020, TPS61024, TPS61025

TPS61026, TPS61027, TPS61028

TPS61029

SLVS451F –SEPTEMBER 2003–REVISED APRIL 2012

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LAYOUT CONSIDERATIONS

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents

and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as

well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground

tracks. Use a common ground node for power ground and a different one for control ground to minimize the

effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. The

most critical current path for all boost converters is from the switching FET, through the synchronous FET, then

the output capacitors, and back to ground of the switching FET. Therefore, both output capacitors and their

traces should be placed on the same board layer as close as possible between the IC’s VOUT and PGND pin.

Especially at output voltages above 4.5V, adding an RC snubber from the SW pin to PGND pin may assist in

further reducing the parasitic inductance impact of this critical current path. Refer to the application report

(SLVA255) for details of implementing a snubber. In addition, the input capacitor should be placed as close as

possible between the IC’s VBAT and PGND pin. Placing the inductor close to the SW pin with a wide but short

trace helps to improve efficiency and minimize EMI. To lay out the control ground, it is recommended to use

short traces as well, separated from the power ground traces. This avoids ground shift problems that can occur

due to superimposition of power ground current and control ground current. The recommended layout is shown

in Figure 23.

Figure 23. PCB Layout Recommendation

Product Folder Link(s): TPS61020 TPS61024 TPS61025 TPS61026 TPS61027 TPS61028 TPS61029