Datasheet

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I
AUX
(100%) +
ƪ
ǒ
1.254
R
IS
) 1.276 10
*6
Ǔ
8000
3.5 10
*6
ƫ
10
(3)
I
AUX
(70%) +
ƪ
ǒ
1.254
R
IS
) 1.276 10
*6
Ǔ
6000
3.5 10
*6
ƫ
9.333
(4)
I
AUX
(40%) +
ƪ
ǒ
1.254
R
IS
) 1.276 10
*6
Ǔ
4000
3.5 10
*6
ƫ
8
(5)
I
AUX
(20%) +
ƪ
ǒ
1.254
R
IS
) 1.276 10
*6
Ǔ
2000
3.5 10
*6
ƫ
8
(6)
SERIAL INTERFACE
Dataline
stable;
datavalid
DATA
CLK
Change
ofdata
allowed
TPS60251
SLVS767C – APRIL 2007 – REVISED NOVEMBER 2007
R
IS
also affects the current for the auxiliary application. The four current levels (20%, 40%, 70%, and 100%) are
determined by the following equations:
The serial interface is compatible with the standard and fast mode I
2
C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the WLED driver solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
V
CC
remains above UVLO2 (typical 1.3V) and ENA is high.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS60251 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS60251 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. Setup and hold times must be taken into account. During read operations, a master
must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked
out of the slave. In this case, the slave TPS60251 device must leave the data line high to enable the master to
generate the stop condition.
Figure 15. Bit Transfer on the Serial Interface
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