Datasheet
TPS60250
TPS60252
www.ti.com
............................................................................................................................................................ SLVS769C – APRIL 2007 – REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS (continued)
V
I
= 3.5 V, T
A
= – 40 ° C to 85 ° C, typical values are at T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
hys
Under-voltage lockout hysterisis UVLO1 210 mV
V
I
= 3 V, C
O
= 1 µ F,
T
S
Soft start time
(3)
0.5 ms
I
MAIN_LED
= 15 mA × 4
CHARGE PUMP
V
out
Overvoltage limit 6.5 V
F
s
Switching frequency 750 kHz
× 1 Mode, (V
I
– V
O
)/I
O
1.2
R
O
Open loop output impedance Ω
× 1.5 Mode, (V
I
× 1.5 – V
O
)/I
O
V
I
= 3.0V (I
O
=
3.5 5.0
120 mA)
CURRENT SINK
Current matching of sub LEDs at light I
SUB_LED
= 100 µ A × 2, V
DXX
= 0.4 V
K
m_sub
0 ± 2%
load condition
(4)
I
MAIN_LED
= 15 mA × 4,
K
m_main
LED to LED Current matching
(5)
± 0.1% ± 5%
3.0 V ≤ V
I
≤ 4.2 V
K
a
Current accuracy I
LED
= 15 mA ± 7%
Main and Sub Display Current Register =
Maximum LED current of DM1-4 and
I
D_MS
0 × 01&2(111111), 25.5 mA
DS1-2
V
DXX
= 0.2 V
I
D_DM5
Maximum LED current of DM5 Aux Display Current Register = 0 × 03 (XXXX11) 80 mA
V
DropOut
LED Drop out voltage See
(6)
80 120 mV
1 × Mode to 1.5 × mode transition V
DXX
Falling, 15 mA × 4 measured on the
V
TH_GU
85 100 120 mV
threshold voltage
(7)
lowest V
DXX
Input voltage hysteresis for 1.5 × to 1 × Measured as V
I
– (V
O
– V
DXX_MIN
), I
MAIN_LED
=
V
TH_GD
550 mV
mode transition 15 mA × 4
SERIAL INTERFACE TIMING REQUIREMENTS
f
max
Clock frequency 400 kHz
t
wH(HIGH)
Pulse duration, clock high time 600 ns
t
wL(LOW)
Pulse duration, clock low time 1300 ns
t
r
DATA and CLK rise time 300 ns
t
f
DATA and CLK fall time 300 ns
High time (repeated) START
t
h(STA)
condition(after this period the first clock 600 ns
pulse is generated)
Setup time for repeated START
t
su(STA)
600 ns
condition
t
h(DATA)
Data input hold time 0 ns
t
su(DATA)
Data input setup time 100 ns
t
su(STO)
STOP condition setup time 600 ns
t
(BUF)
Bus free time 1300 ns
I
2
C COMPATIBLE INTERFACE VOLTAGE SPECIFICATION (SCLK, SDAT, VIO)
V
IL
Low-leveI input voltage 3.0 V ≤ V
I
≤ 6.0 V 0 0.5 V
V
IH
High-level input voltage 3.0 V ≤ V
I
≤ 6.0 V 1.1 V
V
OL
Low-level output voltage I
LOAD
= 2 mA 0.4 V
(3) Measurement Condition: From enabling the LED driver to 90% output voltage after V
I
is already up.
(4) LED current matching is defined as: (I
SUB_LED_WORST
– I
AVG_SUB
) / I
AVG_SUB
(5) LED to LED Current Matching is defined as: (I
MAIN_LED_WORST
– I
AVG_MAIN
) / I
AVG_MAIN
(6) Dropout Voltage is defined as V
DXX
(WLED Cathode) to GND voltage at which current into the LED drops 10% from the LED current at
V
DXX
= 0.2 V, WLED current = 15 mA × 4.
(7) As V
I
drops, V
DXX
eventually falls below the switchover threshold of 100mV, and TPS60250/2 switches to 1.5 × mode. See the Operating
Principle section for details about the mode transition thresholds.
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