Datasheet


   
   
SLVS216B − JUNE 1999 − JUNE 2008
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at C
IN
= 15 µF, C
1F
= C
2F
= 2.2 µF
†
, C
O
= 33 µF, T
C
= −40°C to 85°C,
V
IN
= 3 V, V
FB
= V
O
, V
ENABLE
= V
IN
, V
SKIP
= V
IN
or 0 V and V
COM
= V
CLK
= V
SYNC
= 0 V (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage
2.7 5.4 V
I
O(MAX)
Maximum output current 150 mA
V
O
Output voltage
2.7 V < V
IN
< 3 V, 0 < I
O
< 75 mA,
V
O(Start-Up)
= 5 V, T
C
= 25°C
4.8 5 5.2
V
V
O
Output voltage
3 V < V
IN
< 5 V, 0 < I
O
< 150 mA
4.8 5 5.2
V
5 V < V
IN
< 5.4 V, 0 < I
O
< 150 mA 4.8 5 5.25
V
O(RIP)
Output voltage ripple I
O
= 150 mA, V
SKIP
= 0 V 10
‡
mV
PP
I
O(LEAK)
Output leakage current V
IN
= 3.6 V, V
ENABLE
= 0 V 1 µA
I
Q
Quiescent current
V
SKIP
= V
IN
= 3.6 V 60 90 µA
I
Q
Quiescent current
(no-load input current)
V
SKIP
= 0 V, V
IN
= 3.6 V
2.8 mA
I
DD(SDN)
Shutdown supply current V
IN
= 3.6 V, V
ENABLE
= 0 V 0.05 1 µA
f
OSC(int)
Internal switching frequency V
IN
= 3.6 V 200 300 400 kHz
f
OSC(ext)
External clock frequency V
SYNC
= V
IN
,V
IN
= 2.7 V to 5.4 V 400 600 800 kHz
External clock duty cycle V
SYNC
= V
IN
,V
IN
= 2.7V to 5.4 V 20% 80%
Efficiency I
O
= 75 mA 80%
V
INL
Input voltage low,
ENABLE, SKIP, COM, CLK, SYNC
V
IN
= 2.7 V
0.3 ×
V
IN
V
V
INH
Input voltage high,
ENABLE, SKIP, COM, CLK, SYNC
V
IN
= 5.4 V
0.7 ×
V
IN
V
I
I(LEAK)
Input leakage current,
ENABLE, SKIP, COM, CLK, SYNC
V
ENABLE
= V
SKIP
= V
COM
= V
CLK
=
V
SYNC
= V
GND
or V
IN
0.01 0.1 µA
Output load regulation
V
O
= 5 V, 1 mA < I
O
< 150 mA
T
C
= 25°C
0.002 %/mA
Output line regulation
3 V < V
IN
< 5 V, V
O
= 5 V,
I
O
= 75 mA, T
C
= 25°C
0.6 %/V
Short circuit current
V
IN
= 3.6 V V
O
= 0 V,
T
C
= 25°C
150 mA
†
Use only ceramic capacitors with X5R or X7R dielectric as flying capacitors.
‡
Achieved with C
O
= 22 µF + 10 µF X5R dielectric ceramic capacitor