Datasheet

TPS59640EVM
CPU Output Load Insertion with
OSR/USR = 20 k - Min
Test Condition: 12Vin, 1.05V/0A
CPU 2-Phase on board dynamic load
CH1: DYN_C
CH2: CSW1
CH3: CSW2
CH4: Vcore
TPS59640EVM
CPU Output Load Release with
OSR/USR = 20 k - Min
Test Condition: 12Vin, 1.05V/0A-51A
CPU 2-Phase on board dynamic load
CH1: DYN_C
CH2: CSW1
CH3: CSW2
CH4: Vcore
Performance Data and Typical Characteristic Curves www.ti.com
Figure 41. CPU2 Output Load Insertion With OSR/USR Figure 42. CPU2 Output Load Release With OSR/USR
20k (Min) 20k (Min)
Figure 43. CPU2 Bode Plot at 12Vin, 1.05 V/55 A
38
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796–January 2012
Power System
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