Datasheet
www.ti.com
Test Procedure
3. Measure V3: VCCIO at J25 and A1: 12Vin input current.
4. Vary VDDQ LOAD from 0 Adc to 15 Adc; VCCIO must remain in the load regulation.
5. Vary 12VBAT from 9 V to 20 V; VCCIO must remain in the line regulation.
6. Push S1 to OFF position to disable VCCIO controller.
7. Decrease LOAD to 0 A, and disconnect the LOAD from terminal J24.
8. Disconnect V3 from J25.
7.2 Equipment Shutdown
1. Shut down load.
2. Shut down 12VBAT and 5Vin.
3. Shut down oscilloscope.
4. Shut down host computer.
31
SLUU796– January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated