Datasheet

1
17
1
1
17
R170
8. 06k
C192
0.1uF
10.0k
R171
TP73
TP82
TP75 TP72
D8
RED
R152
100k
1uF
C190
TP86
3.3V LDO
R175
0.005
0.05
R168
R155
30.1k
R151
15.0k
R169
0.05
C177
10uF
TP84
0.1uF
C182
R172
0. 005
R162
0.01
100k
R173
TP77
+
C179
1
R159
TP78
10.0k
R
174
TP74
TP79
C181
10uF
330
R176
RED
D5
R178
330
R179
330
2.2uF
C184
0.05
R166
30.1k
R154
0.01
R167
TP71
R164
0.05
10.0k
R165
Q10
CSD16407Q5
1.8V LDO
C189
0.01uF
C191
0.1uF
5V Bias Voltage Input
VBAT Voltage Input:
9V- 20V
U8:C
U8:B
C188
1uF
Not used
D4
RED
CSD16407Q5
Q12
CSD16407Q5
Q13
C183
10uF
R157
1
C187
1uF
TP83
0.0
1
R161
C193
0.1uF
D6
BAT54
+
C178
1
R158
1
R160
TP80
D7
RED
330
R177
U8:D
U8:A
CD74HCT08D
UCC27324D
U9
UCC27324D
U10
C194
1uF
VCCIO, GPU and CPU Dynamic Load:
1. Switch to "ON" position to enable the Dynamic Load
2. Switch to "OFF" position to disable the Dynamic Load
(Default )
C180
0. 1uF
C185
0.1uF
TP85
C186
0.01uF
R156
51.1k
TP76
TP81
R153
2. 00k
0.05
R163
VCCIO_DL
GPU_DL
CPU_DL1
CPU_DL2
Q11
CSD16407Q5
150mA LDO
LDOs and Dynamic Loads
1.2V LDO
S2
5
OUT
4
NR/FB
1
IN
3
EN
2
GND
U7
TPS71712DCK
S
3
3
VIN1
2
VIN1
7
SEQUENCE
8
GND
9
VIN2
10
VIN2
1
NC
11
NC
12
VOU T2
13
VOU T2
14
VSENSE2
1
6
PG D_1
17
VSENSE1
18
VOU T1
19
VOU T1
20
N C
Pw rPad
4
MR2
5
MR1
6
ENA
BLE
1 5
RESET
TPS70102PWP
U6
www.ti.com Schematic
Figure 10. TPS59640EVM-751 Schematic (8 of 13)
15
SLUU796– January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
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