Datasheet

15
1
14
1
15
1
1
1
1
1
1
1
1
1
14
1
1
Not used
R135
10
10
R132
TP53
R123
1.00k
C125
0.01uF
TP51
TP48
1
C148
2.2uF
C127
C150
1
TP56
2.21
R125
1
C126
TP50
R128
10.5k
0.1uF
C119
C124
1nF
TP49
J25
C120
0. 1uF
C128
22uF
22uF
C146
C115
10uF
C130
C144
22uF
C131 C118
1nF
C142
22uF
C134
R127
C139
TP55
+
C123
+
C121
330uF
S1: VCCIO Enable Pin
To proces sor
0
R134
R122
10.0k
R119
180
R120
180
C147
C149
To controller
0
R131
R124
2.21
TP52
R121
1.00k
C113
1nF
VCCIO Power Supply
R129
0
0.56uH
L5
R133
0
D2
GREEN
Q5
BSS123
Q6
BSS123
R126
C129
C143
22uF
R130
37.4k
10uF
C114
C116
10uF
C132
22uF
C133
22uF
C135
22uF
C137
22uF
C138
22uF
C141
22uF
C145
TP57
C117
10uF
TP54
C136
C140
22uF
+
330uF
C122
VCCIO Output Selection:
1. Jumper shorts on pin1 and pin2 of J23 to set VCCIO: 1.05V(Defau
lt)
2. Jumper shorts on pin2 and pin3 of J23 to set VCCIO: 1.00V
D1
GREEN
www.ti.com Schematic
Figure 8. TPS59640EVM-751 Schematic (6 of 13)
13
SLUU796– January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
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