User's Guide SLUU796 – January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System The TPS59640EVM-751 evaluation module (EVM) is a complete solution for the Intel™ IMVP-7 Serial VID (SVID) Power System from a 9-V to 20-V input bus. This EVM uses the TPS59640 for IMVP-7 3-Phase CPU and 1-Phase GPU Vcore, TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4 memory rail (1.2VDDQ, 0.6VTT, and 0.6VTTREF).
www.ti.com 5 TPS59640EVM-751 Schematic (3 of 13)............................................................................... 10 6 TPS59640EVM-751 Schematic (4 of 13)............................................................................... 11 7 TPS59640EVM-751 Schematic (5 of 13)............................................................................... 12 8 TPS59640EVM-751 Schematic (6 of 13)...............................................................................
www.ti.com 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 .............................................................................. CPU1 Output Load Insertion With OSR/USR 20k (Min) ............................................................. CPU1 Output Load Release With OSR/USR 20k (Min) ............................................................. CPU1 Bode Plot at 12Vin, 1.05 V/33 A ...............
Description www.ti.com List of Tables 1 TPS59640EVM-751 Electrical Performance Specifications ........................................................... 6 2 Current Limit Trip Selection .............................................................................................. 24 3 CPU Frequency Selection ................................................................................................ 25 4 GPU Frequency Selection ..................................................................
TPS59640EVM-751 Power System Block Diagram www.ti.com 2 TPS59640EVM-751 Power System Block Diagram IMVP7 TPS59640 9-20VBAT CPU Core (94A) 48 Pin 6x6 QFN TPS51219 SVID GPU Core (33A) Power Block 16 Pin 3x3 QFN TPS51916 20 Pin 3x3 QFN TPS70102PWP 5Vin 20 Pin PWP VCCIO: 1.05V/15A DDR3L/DDR4 Memory Rail VDDQ: 1.2V/15A VTT: 0.6V/2A, VTTREF: 0.6V/10mA 1.8V/500mA 3.
Electrical Performance Specifications www.ti.com IMVP7 TPS59640 + TPS51219 + TPS51916 POWER EVM with CSD87350Q5D Powerblocks CPU/GPU VR_ON Connections for electronic loads CSD87350Q5D OCL, FSW, OSR selection CPU Core TPS59640 TPS51219 VCCIO GPU CORE Sandy Bridge CPU socket (not populated) Intel SVID GUI from USB TPS51916 DDR3L/DDR4 Memory Rail Figure 2. TPS59640EVM-751 EVM Illustration 3 Electrical Performance Specifications Table 1.
Electrical Performance Specifications www.ti.com Table 1. TPS59640EVM-751 Electrical Performance Specifications (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GPU (TPS59640) Output voltage Vcore Output voltage regulation SVID: address:01 GPU, payload: 1.23 V 1.23 Line regulation –3.9 Load regulation (droop) load line Output voltage ripple VBAT = 12 V, 1.
3 8 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Copyright © 2012, Texas Instruments Incorporated 5 200k R21 TP17 C1 6 0.33uF TP10 C28 220nF R16 150k R14 169k C23 1uF TP19 2 R5 1 R24 309k TP7 100pF C26 4.12k R22 8.45k R6 C14 100pF R3 54.9 R26 0 TP1 4 R25 R15 2.21 R11 2.
SLUU796 – January 2012 Submit Documentation Feedback TP24 Copyright © 2012, Texas Instruments Incorporated 22uF 22uF 22uF C 41 C31 10uF 22uF C40 1uF C34 C30 10uF 22uF C54 22uF C55 22uF C56 C39 2.21 R27 C29 10uF C53 TP25 TP21 TP20 22uF C43 22uF C57 C42 TP23 22uF C58 C33 1nF 22uF C38 2.2uF C32 10uF 1 C46 C47 10uF 10uF 10uF C61 22uF C62 Not used 10uF 10uF C45 22uF C60 0 R30 22uF C59 C44 TP26 R28 2.
TP33 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Copyright © 2012, Texas Instruments Incorporated 22uF C87 TP34 TP 29 1 C77 TP28 1 C78 22uF C8 9 1uF 2.21 1 C79 C69 10uF C73 C68 10u F R33 22uF C88 C67 10uF 22uF C90 1 C80 C76 2.2uF C70 10uF 1 C91 1 C82 22uF C92 C81 TP35 2.21 R31 22uF TP3 0 C71 1nF 1 C93 1 1 C94 Not used 22uF C83 0 R34 22u F C84 2 2uF C95 22uF C85 22uF C96 TP31 22uF C86 1 C75 1 R3 2 1 1 L4 0.
SLUU796 – January 2012 Submit Documentation Feedback C98 33nF Copyright © 2012, Texas Instruments Incorporated C102 33nF R69 28.7k C110 33nF 0 R70 0 R68 162k RT6 100k 0 R64 17.8k C106 33nF 0 R56 0 R52 R66 R6 3 28.7k RT5 100k R51 28.7k R65 R62 162k 17.8k R55 R50 162k 0 RT4 100k 17.8k 0 R41 R45 R39 28.7k R44 R38 162k 0 17.
11 12 R84 R87 R90 R93 R96 R99 R102 R105 R108 R111 R114 R117 39.2k 30.1k 150k 75.0k 56.2k 39.2k 30.1k 24.3k 20.0k 100k 20.0k 24.3k 56.2k R78 R81 R75 R72 75.0k 150k 100k Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Copyright © 2012, Texas Instruments Incorporated 13 12 11 12 TP47 TP46 24.3k 20.0k R116 R107 R110 R113 R98 R101 R104 R95 150k 100k 75.0k 56.2k 39.2k 30.1k R89 R92 R86 30.1k 24.3k 20.0k R77 R80 R83 R71 R74 75.0k 56.2k 39.
SLUU796 – January 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Q5 BSS123 14 TP50 To proces sor D1 GREEN R119 180 1 15 14 0 R134 0 R133 R128 10.5k 1 R126 C119 0.1uF R123 1.00k C124 1nF TP53 Q6 BSS123 TP49 C125 0.01uF 15 To controller J25 R130 37.4k 1.00k R121 C113 1nF S1: VCCIO Enable Pin VCCIO Output Selection: 1. Jumper shorts on pin1 and pin2 of J23 to set VCCIO: 1.05V(Default) 2. Jumper shorts on pin2 and pin3 of J23 to set VCCIO: 1.
Q8 BSS123 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Copyright © 2012, Texas Instruments Incorporated 0 R 150 0 R 148 C160 2.2uF D3 GREEN R136 180 C157 10uF R137 10.0k TP60 16 1 TP70 C164 0.1uF To controller J29 C163 0.22uF C176 1nF R141 37.4k 0 R146 C156 0.1uF R142 2.21 R138 10.0k S3/S5 Enable Control, See datasheet for detail Not used R149 20.0k R147 10.0k R140 1.00k R139 10.0k 16 C 162 2.2uF TP61 1 C174 T P67 2.
SLUU796 – January 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated C189 0.01uF R173 100k R170 8.06k C192 0.1uF 0.1uF C191 D6 BAT54 R171 10.0k VCCIO_DL GPU_DL CPU_DL1 CPU_DL2 1 C179 R158 1 5V Bias Voltage Input TP77 + VBAT Voltage Input: 9V- 20V C193 0.1uF R165 10.0k R159 1 R174 10.0k TP79 C178 TP74 1 TP78 + TP73 17 R160 1 TP80 TP82 17 1 C180 0.
1 R185 C195 1nF R186 100 18 1 J35 R192 3.01k Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID Power System Copyright © 2012, Texas Instruments Incorporated Q15 BSS123 D9 GREEN VR_ON R203 180 Q16 BSS123 D10 GREEN TP90 C_PGOOD R204 180 R206 10.0k C197 10pF C198 10pF C196 0.1uF Q17 BSS123 D12 GREEN TP89 G_PGOOD R205 180 R202 10.0k 1 18 R208 10.0k TP88 R199 330 1 1 C199 0.1uF Support and Pull-ups 1 10.0k 10.
Schematic R211 75.0 1 R210 1 R212 130 R213 43.2 1 Not used uC Socket Main www.ti.com Figure 12.
Schematic 1 1 Not used uC Socket Others www.ti.com Figure 13.
SLUU796 – January 2012 Submit Documentation Feedback J42 Copyright © 2012, Texas Instruments Incorporated 1 20 J43 R221 475 D13 GREEN USB Connector DM V+ VNC DP 19 FB1 J41 R222 2.21k R216 33.2 R215 33.2 TP91 TP92 20 19 1 R214 1.50k C202 0.1uF C206 22pF C208 0.01uF U14 TUSB3410RHB For Internal software developmenet 5V Bias option: 1. Jumper shorts on J41, 5V Bias used from USB. If USB 5V is used, external 5V supply from 2.
C210 0.1uF C211 0.1uF 20 C214 0.1uF U15:B TMS320F2806PZS C213 0.1uF C215 0.1uF 47 GPIO 0 44 GPIO1 45 GPIO2 48 GPIO3 51 GPIO4 53 GPIO5 56 GPIO6 58 GPIO7 60 GPIO8 61 GPIO9 64 GPIO10 70 GPIO11 1 GPIO 12 95 GPIO13 8 GPIO14 9 GPIO15 50 GPIO16 C209 0.
Test Setup www.ti.com 5 Test Setup 5.1 Test Equipment 5.1.1 Personal Computer (Host Computer) Microsoft Windows™ XP or newer with available USB port 5.1.2 USB Cable The USB cable: standard USB_A to USB_B, 5-pin, mini-B cable. See the Figure 16 illustration. Figure 16. USB Cable 5.1.3 TPS59640 USB Driver and SVID GUI Installation Copy the file swrc094f.zip to the host computer. Copy the file TI-SVID-GUI_1_5_0_1 exe to the host computer. Extract setup.exe from the aforementioned .zip file.
Test Setup 5.1.7 www.ti.com Oscilloscope A digital or analog oscilloscope can be used to measure the output ripple. The oscilloscope must be set for 1-MΩ impedance, 20-MHz bandwidth, AC coupling, 2-µs/division horizontal resolution, 50-mV/division vertical resolution. Test points TP27 and TP37 can be used to measure the output ripple voltage for CPU and GPU. Do not use a leaded ground connection as this can induce additional noise due to the large ground loop. 5.2 Recommended Wire Gage 1.
Test Setup www.ti.com 12VBAT DC Source - + 5Vin DC Source + - Load VCCIO USB Cable A + - + - - + V3 CPU - + - + A1 V2 - + - V1 + + - TEXAS INSTRUMENTS B GPU + Host Computer + VDDQ Figure 17. TPS59640EVM-751 Recommended Test Setup 5.4 USB Cable Connections A standard USB_A and 5-pin mini_B USB cable is required to connect the host computer to J42 USB port (left bottom side). A green LED (D13) lights up near the USB port on the EVM. This indicates that the USB cable is connected.
Configuration 5.6 www.ti.com Output Connections 1. Connect the load to J1, J5, and J6, and set the load to constant resistance mode to sink 0 Adc before 5Vin and 12VBAT are applied. This is for CPU operation. 2. Connect a voltmeter V3 at J14 to measure CPU Vcore sense voltage. 6 Configuration All jumper selections must be made prior to applying power to the EVM. The user can configure this EVM per the following configurations. 6.1 6.1.
Configuration www.ti.com 6.1.2 CPU Frequency Selection (J18) The operating frequency can be set by J18 Default setting: 300 kHz for CPU. Table 3. CPU Frequency Selection 6.1.3 Jumper Set to Connected Resistor CPU Left (1-2 pin shorted) 150k 600 kHz Second (3-4 pin shorted) 100k 550 kHz Third (5-6 pin shorted) 75k 500 kHz Fourth (7-8 pin shorted) 56.2k 450kHz Fifth (9-10 pin shorted) 39.2k 400kHz Sixth (11-12 pin shorted) 30.1k 350kHz Seventh (13-14 pin shorted) 24.
Configuration 6.1.5 www.ti.com GPU Overshoot/Undershoot Reduction Selection (J22) The overshoot/undershoot reduction can be set by J22 GSKIP. Default setting: Max. Table 6. GPU Overshoot/Undershoot Reduction Selection 6.1.6 Jumper Set to Connected Resistor Right (1-2 pin shorted) 150k CPU Max Second (3-4 pin shorted) 100k Level 7 Third (5-6 pin shorted) 75k Level 6 Fourth (7-8 pin shorted) 56.2k Level 5 Fifth (9-10 pin shorted) 39.2k Level 4 Sixth (11-12 pin shorted) 30.
Configuration www.ti.com 6.1.9 IMVP-7 VR_ON Enable Selection (S4) The IMVP-7 CPU/GPU can be enabled and disabled by S4. Default setting: Push S4 to OFF position to disable both CPU and GPU. Table 10. VR_ON Enable Selection 6.2 6.2.1 Switch Set to VR_ON Selection Push S4 to ON position Enable IMVP-7 CPU/GPU Vcore Push S4 to OFF position Disable IMVP-7 CPU/GPU Vcore 1.2VDDQ, 0.6V VTT and 0.
Test Procedure www.ti.com 7 Test Procedure 7.1 Line/Load Regulation and Efficiency Measurement Procedure 7.1.1 CPU 1. Set up EVM as described in Section 5.3, Section 5.4, Section 5.5, Section 5.6, and Figure 17. 2. Ensure no jumper shorts are on J46. 3. Ensure all other jumpers configuration settings in this section before 5Vin and 12VBAT are applied. 4. Ensure load is set to constant resistance mode and to sink 0 Adc. 5. Ensure S1 and S4 are in OFF position. 6.
Test Procedure www.ti.com Figure 18. TPS59640EVM-751 CPU GUI Setup Window 7.1.2 GPU Connect the LOAD to GPU terminal J11 and V3 at J16. Ensure correct polarity. Add scope probe on the TP37 for GPU G_Vcore ripple measurement. Push S4 to ON position to enable the VR_ON of TPS59640. The VR_ON LED lights up. Now you are ready to send SVID commends for GPU. Using the pulldown menu: Address: 01 GPU, Commend: SetVIDslow, Payload: 1.23V 5. Click send Commend, and GPU GPOOD LED lights up.
Test Procedure www.ti.com 14. Disconnect the USB cable between host Computer and EVM. Figure 19. TPS59640EVM-751 GPU GUI Setup Window 7.1.3 1. 2. 3. 4. 5. 6. 7. 8. VDDQ Connect the LOAD to VDDQ terminal J28 and V3 at J29. Ensure correct polarity. Remove jumper from J27 from pin 2 and pin 3, and put this jumper on pin 1 and pin 2 of J27 to enable S5 of VDDQ controller. VDDQ PGOOD LED lights up.
Test Procedure www.ti.com 3. 4. 5. 6. 7. 8. 7.2 Measure V3: VCCIO at J25 and A1: 12Vin input current. Vary VDDQ LOAD from 0 Adc to 15 Adc; VCCIO must remain in the load regulation. Vary 12VBAT from 9 V to 20 V; VCCIO must remain in the line regulation. Push S1 to OFF position to disable VCCIO controller. Decrease LOAD to 0 A, and disconnect the LOAD from terminal J24. Disconnect V3 from J25. Equipment Shutdown 1. 2. 3. 4. Shut down Shut down Shut down Shut down load. 12VBAT and 5Vin. oscilloscope.
Performance Data and Typical Characteristic Curves 8 www.ti.com Performance Data and Typical Characteristic Curves Figure 20 through Figure 91 present typical performance curves for TPS59640EVM-751. Jumpers are set to default locations; see Section 6 of this user’s guide 8.1 CPU3-Phase Operation 95 1.1 VI = 9 V SPEC (max) VI = 12 V 90 1.05 20 Vin Vout (V) IO - Output Voltage - V 9 Vin Vout (V) Efficiency - % 85 VI = 20 V 80 75 12 Vin Vout (V) 0.95 SPEC (nom) 0.9 SPEC (min) 0.
Performance Data and Typical Characteristic Curves www.ti.com TPS59640EVM CPU Switching Node Test condition: 12 Vin, 105 V 90 A CPU 3 Phase operation TPS59640EVM Dynamic VID: Set VID-Set VID-Slow Test condition: 12 Vin, 105 V-0.6 V, 0.5 A CPU 2 Phase operation CH1: CSW1 CH1: CSW1 CH2: CSW2 CH2: CSW2 CH3: Vcore CH3: VSW3 CH4: VDIO CH4: Vcore Ripple Figure 24. CPU3 Switching Node (Ripple) TPS59640EVM Dynamic VID: set VID-Fast/Set VID-Fast Test condition: 12 Vin, 105 V-06 V, 0.
Performance Data and Typical Characteristic Curves TPS59640EVM CPU Output Load Insertion with OSR/USR = 20 k (Min) www.ti.com TPS59640EVM CPU Output Load Release with OSR/USR = 20 k (Min) Test condition: 12 Vin, 105 V/0 A-51 A CPU 3 Phase on board dynamic load CH1: CSW1 Test condition: 12 Vin, 105 V/0 A-51 A CPU 3 Phase on board dynamic load CH1: CSW1 CH2: CSW2 CH2: CSW2 CH3: VSW3 CH3: CSW3 CH4: Vcore CH4: Vcore Figure 28. CPU3 Output Load Insertion With OSR/USR20k (Min) Figure 29.
Performance Data and Typical Characteristic Curves www.ti.com Figure 31. CPU3 MOSFET Figure 32. CPU3 IC Test condition: CPU3 12Vin, 1.
Performance Data and Typical Characteristic Curves 8.2 www.ti.com CPU 2-Phase Operation 1.1 95 VI = 12 V VI = 9 V 90 Efficiency - % 85 VO - Output Voltage - V 1.05 VI = 20 V 80 75 0.95 12 Vin Vout - V 20 Vin Vout - V 9 Vin Vout - V 0.9 70 65 0 1 5 10 15 20 25 30 35 40 IO - Output Current - A 45 50 55 0.85 0 Figure 33.
Performance Data and Typical Characteristic Curves www.ti.com TPS59640EVM CPU Switching Node Test condition: 12 Vin, 105 V 50 A CPU 2 Phase operation Test Condition: 12Vin,VID: 1.05V-0.6V, 0.5A TPS59640EVM CPU 2 Phase operation Dynamic VID: Set VID-Slow/Set VID-Slow CH1: CSW1 CH1: CSW1 CH2: CSW2 CH2: CSW2 CH3: Vcore CH4: VDIO CH3: Vcore Ripple Figure 37. CPU2 Switching Node (Ripple) Test Condition: 12Vin,VID: 1.05V-0.6V, 0.
Performance Data and Typical Characteristic Curves TPS59640EVM CPU Output Load Insertion with OSR/USR = 20 k - Min Test Condition: 12Vin, 1.05V/0A CPU 2-Phase on board dynamic load www.ti.com TPS59640EVM CPU Output Load Release with OSR/USR = 20 k - Min Test Condition: 12Vin, 1.05V/0A-51A CPU 2-Phase on board dynamic load CH1: DYN_C CH1: DYN_C CH2: CSW1 CH2: CSW1 CH3: CSW2 CH3: CSW2 CH4: Vcore CH4: Vcore Figure 41. CPU2 Output Load Insertion With OSR/USR Figure 42.
Performance Data and Typical Characteristic Curves www.ti.com Figure 44. CPU2 MOSFET Figure 45. CPU2 IC Test condition: CPU2 12Vin, 1.
Performance Data and Typical Characteristic Curves 8.3 www.ti.com CPU 1-Phase Operation 1.1 95 VI = 9 V VI = 12 V 1.05 VO - Output Voltage - V Efficiency - % 90 85 VI = 20 V 80 1 12 Vin Vout - V 20 Vin Vout - V 0.95 9 Vin Vout - V 75 SPEC - min SPEC - nom SPEC - max 70 0.9 0 5 10 15 20 25 IO - Output Current - A 30 35 Figure 46. CPU1 Efficiency TPS59640EVM CPU VDIO Turn on Test Condition: 12Vin, 1.
Performance Data and Typical Characteristic Curves www.ti.com TPS59640EVM CPU Switching Node Test Condition: 12Vin, 1.05V/30A CPU 1 Phase operation TPS59640EVM CPU Output Ripple Test Condition: 12Vin, 1.05V/30A CPU 1 Phase operation CH1: CSW1 CH1: CSW1 CH2: Vcore Ripple Figure 50. CPU1 Switching Node TPS59640EVM Test Condition:12Vin,VID:1.05V-0.6V, 0.5A Dynamic VID: Set VID-Slow/Set VID-Slow CPU 1 Phase operation TPS59640EVM Dynamic VID:Set VID-Fast/Set VID-Fast Test Condition: 12Vin,VID: 1.05V-0.
Performance Data and Typical Characteristic Curves www.ti.com TPS59640EVM CPU Output Load Insertion with OSR/USR = 20 k - Min Test Condition: 12Vin,VID: 0.6V-1.05V, 0.5A TPS59640EVM CPU 1 Phase operation Dynamic VID: Set VID-Fast/Set VID-Decay Test Condition: 12Vin, 1.05V/0A-32A CPU 1-Phase on board dynamic load CH1: VDIO CH1: DYN_C CH2: CSW1 CH2: CSW1 CH3: Vcore CH4: Vcore CH4: CPGOOD Figure 54.
Performance Data and Typical Characteristic Curves www.ti.com Figure 57. CPU1 Bode Plot at 12Vin, 1.05 V/33 A Figure 58. CPU1 MOSFET Figure 59. CPU1 IC Test condition: CPU1 12Vin, 1.
Performance Data and Typical Characteristic Curves 8.4 www.ti.com GPU Operation 95 1.3 VI = 9 V VI = 12 V 85 1.25 VO - Output Voltage - V Efficiency - % 90 VI = 20 V 80 1.15 75 70 1.2 12 Vin Vout - V 20 Vin Vout - V 9 Vin Vout - V 1.1 SPEC - min SPEC - nom SPEC - max 0 5 10 15 20 25 IO - Output Current - A 30 35 1.05 0 Figure 60. GPU Efficiency TPS59640EVM CPU VDIO Turn on Test Condition: 12Vin, 1.23V/20A CPU operation 5 30 35 Figure 61.
Performance Data and Typical Characteristic Curves www.ti.com TPS59640EVM GPU Switching Node Test Condition: 12Vin, 1.23V/30A GPU operation TPS59640EVM GPU Output Ripple Test Condition: 12Vin, 1.23V/30A GPU operation CH1: GSW CH1: GSW CH2: G_Vcore Ripple Figure 64. GPU Switching Node TPS59640EVM Test Condition:12Vin,VID: 1.23V-0.6V, 0.5A Dynamic VID: Set VID-Slow/Set VID-Slow GPU 2 Phase operation TPS59640EVM Dynamic VID: Set VID-Fast/Set VID-Fast Test Condition: 12Vin,VID: 1.23V-0.6V, 0.
Performance Data and Typical Characteristic Curves www.ti.com TPS59640EVM GPU Output Load Insertion with OSR/USR = 20 k - Min TPS59640EVM Test Condition: 12Vin,VID: 0.6V-1.23V,0.5A Dynamic VID: Set VID-Fast/Set VID-Decay GPU operation Test Condition: 12Vin,1.23V/0A-24A GPU on board dynamic load CH1: VDIO CH1: DYN_G CH2: GSW CH2: GSW CH3: G_Vcore CH4: G_Vcore CH4: GPGOOD Figure 68. GPU Dynamic VID: SetVID-Decay/Fast TPS59640EVM GPU Output Load Release with OSR/USR = 20 k - Min Figure 69.
Performance Data and Typical Characteristic Curves www.ti.com Figure 71. GPU Bode Plot at 12Vin, 1.23 V/33 A Figure 72. GPU MOSFET Figure 73. GPU IC Test condition: GPU 12Vin, 1.
Performance Data and Typical Characteristic Curves 8.5 www.ti.com 1.05V VCCIO 100 90 1.08 VI = 9 V 80 VI = 12 V VI = 20 V VO - Output Voltage - V Efficiency - % 70 60 50 40 30 VI = 12 V 1.06 VI = 9 V VI = 20 V 1.04 20 10 0 0.001 0.01 0.1 1 IO - Output Current - A 10 100 1.02 0 Figure 74. 1.05-V Efficiency TPS59640EVM VCCIO Output Start up Test Condition: 12Vin, 1.05V/15A CH1: VCCIO_EN 2 4 14 16 Figure 75. 1.
Performance Data and Typical Characteristic Curves www.ti.com TPS59640EVM VCCIO Switching Node Test Condition: 12Vin, 1.05V/15A TPS59640EVM VCCIO Output Ripple Test Condition: 12Vin, 1.05V/15A CH1: VCCIO_SW CH1: VCCIO Output Ripple Figure 78. 1.05-V Switching Node TPS59640EVM VCCIO Output Transient from DCM to CCM Test Condition: 12Vin, 1.05V/0A-10A CH1: VCCIO Output Voltage TPS59640EVM VCCIO Output Transient from CCM to DCM Test Condition: 12Vin, 1.
Performance Data and Typical Characteristic Curves www.ti.com Figure 82. TPS51219 Thermal Test condition: 12Vin, 1.
Performance Data and Typical Characteristic Curves www.ti.com 8.6 1.2 VDDQ 1.26 100 VI = 9 V 90 1.24 VI = 12 V Efficiency - % 70 VO - Output Voltage - V 80 VI = 20 V 60 50 40 30 20 VI = 12 V 1.22 VI = 20 V 1.20 VI = 9 V 1.18 1.16 10 0 0.001 0.01 0.1 1 IO - Output Current - A 10 Figure 83. 1.2-V Efficiency TPS59640EVM VDDQ Output S5 Start up 1.14 0 2 4 6 8 10 12 IO - Output Current - A 14 16 Figure 84. 1.2-V Load Regulation Test Condition: 12Vin, 1.
Performance Data and Typical Characteristic Curves TPS59640EVM VDDQ Output Switching Node Test Condition: 12Vin, 1.2V/15A CH1: VDDQ SW www.ti.com TPS59640EVM VDDQ Output Ripple CH1: VDDQ Output Ripple Figure 87. 1.2-V Switching Node TPS59640EVM VDDQ Output Transient from DCM to CCM Test Condition: 12Vin, 1.2V/0A-10A Figure 88. 1.
EVM Assembly Drawings and PCB layout www.ti.com Figure 91. TPS51916 Thermal Test condition: 12Vin, 1.2 V/15 A, no airflow 9 EVM Assembly Drawings and PCB layout The following figures (Figure 92 through Figure 101) show the design of the TPS59640EVM-751 printed-circuit board. The EVM has been designed using an eight-layer circuit board with 2 oz o0f copper on outside layers. TEXAS INSTRUMENTS Figure 92.
EVM Assembly Drawings and PCB layout www.ti.com Figure 93. TPS59640EVM-751 Bottom Assembly Drawing (Bottom View) Figure 94.
EVM Assembly Drawings and PCB layout www.ti.com Figure 95. TPS59640EVM-751 Bottom Copper Figure 96.
EVM Assembly Drawings and PCB layout www.ti.com Figure 97. TPS59640EVM-751 Internal Layer 3 Figure 98.
EVM Assembly Drawings and PCB layout www.ti.com Figure 99. TPS59640EVM-751 Internal Layer 5 Figure 100.
EVM Assembly Drawings and PCB layout www.ti.com Figure 101.
Bill of Materials www.ti.com 10 Bill of Materials The EVM major components list according to the schematics shown in Figure 3 to Figure 15. Table 13. Bill of Materials QTY RefDes Description MFR Part Number 3 C1, C28, C163 Capacitor, Ceramic, 220nF, 25V, X7R, 10%, 0603 STD STD 29 C119, C180, C192, C201, C211, C215, C219, C164, Capacitor, Ceramic, 0.
Bill of Materials www.ti.com Table 13. Bill of Materials (continued) QTY 60 MFR Part Number 19 RefDes R12, R13, R26, R30, R34, R42, Resistor, Chip, 0, 1/10W, 1%, 0603 R43, R54, R57, R129, R131, R133, R134, R145, R146, R148, R150, R219, R220 Description STD STD 5 R121, R123, R140, R200, R207 Resistor, Chip, 1.00k, 1/10W, 1%, 0603 STD STD 14 R122, R147, R201, R217, Resistor, Chip, 10.0k, 1/10W, 1%, 0603 STD STD 1 R128 Resistor, Chip, 10.
Bill of Materials www.ti.com Table 13. Bill of Materials (continued) QTY RefDes Description MFR Part Number 6 R77, R78, R79, R101, R102, R103 Resistor, Chip, 75.0k, 1/10W, 1%, 0603 STD STD 2 R8, R23 Resistor, Chip, 15.4k, 1/10W, 1%, 0603 STD STD 6 R80, R81, R82, R104, R105, R106 Resistor, Chip, 56.2k, 1/10W, 1%, 0603 STD STD 6 R83, R84, R85, R107, R108, R109 Resistor, Chip, 39.2k, 1/10W, 1%, 0603 STD STD 8 R86, R87, R88, R110, R111, R112, R154, R155 Resistor, Chip, 30.
Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.