User's Guide SLUU465 – November 2010 An 8-V to 14-V Vin 2010 Atom™ E6xx Tunnel Creek Power System The TPS59610EVM-634 evaluation module (EVM) is a complete solution for the 2010 Atom™ E6xx Tunnel Creek Power System from a 12-V input bus. The EVM uses the TPS59610 for Atom CPU and GPU core, TPS51120 for 5-V and 3.3-V systems, TPS54326 for Topcliff IOH, TPS59124 for DDRII 1.8 V and CPU VTT 1.05 V, TPS51100 for 0.9 V VTT, TPS74801 for CPU 1.5-V PLL, and CPU C6 RAM 1.05 V.
www.ti.com 4 TPS59610EVM-634 Schematic, Sheet 3 of 5 ........................................................................... 9 5 TPS59610EVM-634 Schematic, Sheet 4 of 5 ......................................................................... 10 6 TPS59610EVM-634 Schematic, Sheet 5 of 5 ......................................................................... 11 7 TPS59610EVM-634 Recommended Test Setup ......................................................................
www.ti.com 52 1.8-V Switching Node ..................................................................................................... 31 53 1.8-V Vo Ripple ............................................................................................................ 31 54 1.05-V Efficiency ........................................................................................................... 31 55 1.05-V Load Regulation 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 ................
Description 1 www.ti.com Description The TPS59610EVM-634 is designed to use a regulated 12-V (8-V to 14-V) bus to produce 10 regulated outputs for an Atom™ E6xx Tunnel Creek Power System. The TPS59610EVM-634 is specially designed to demonstrate the TPS59610 Atom E6xx CPU and GPU Vcore regulators while providing a number of test points to evaluate their static and dynamic performance. 1.1 Typical Applications • 1.
Electrical Performance Specifications www.ti.com 3 Electrical Performance Specifications Table 1.
Electrical Performance Specifications www.ti.com Table 1. TPS59610EVM-634 Electrical Performance Specifications (1) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT S 1.2-V IOH(TPS54326) Output voltage Output voltage regulation Output voltage ripple 1.2 Line regulation Load regulation 1% VIN = 12 V, 1.2 Vout, Io = 3 A Output load current 20 0 Output over current Switching frequency Full load efficiency V 0.1% 12 Vin, 1.2 V/3 A mVpp 3 A 4.1 A 700 kHz 75.4% 1.
TP104 SLUU465 – November 2010 Submit Documentation Feedback TP107 © 2010, Texas Instruments Incorporated An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System 7 TP103 RT101 150K 1uF C108 C105 1 R106 6.19k 7 Bits VIDSetting J107 R123 1 VID3_C TP129 TP130 TP131 VID2_C VID1_C VID0_C TP128 VID4_C THERM_C TP113 DROOP_C ISLEW_C TP126 VID5_C TP127 VID6_C VID5_C VID4_C VID3_C VID2_C VID1_C VID0_C VID6_C 2.00k R110 R108 1 TP124 R109 0 AGND_C C104 68pF VREF_C R104 45.
0 R209 AGND TP207 TP204 45.3k TP203 ISLEW_G An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System © 2010, Texas Instruments Incorporated TP227 15 VID4_G VID3_G VID2_G VID1_G VID0_G VID3_G VID4_G TP226 TP230 VID0_G R223 1 TP229 VID1_G R215 100k 5 Bits VIDSetting J207 VID2_G TP213 THERM_G RT201 150K C208 1uF TP205 DROOP_G C205 1 TP228 R210 2.00k R208 1 C204 68pF R206 6.19k VREF_G R204 10.0k R202 U201 J206 12 R211 5.
GND 5Vout J305 GND GND TP304 Vin TP303 C310 10uF TP309 5Vout TP305 Vin GND 1 21 © 2010, Texas Instruments Incorporated + C312 1000pF R308 1 SW_5V TP307 33uF + C305 + R302 10.0k Option input capacitor for hold up + L301 4.7uH C304 22uF C302 C311 + 330uF R301 10.0k 5VEnable J304 18 J301 C308 0.1uF 5V_BIAS TP311 R306 2.
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System © 2010, Texas Instruments Incorporated GND R419 10.0k 330uF R423 10.0k 25 1.05V_C6RAMEnable TP407 R412 1 10 IN OUT 9 2 IN OUT 8 3 PG FB 7 4 D.N.C BIAS 6 5 GND EN 11 1 U403 TPS74801DRC 2 3 4 5 1 PwPd R418 7.87k R416 6.81k R404 75.0k R422 7.87k R420 2.49k C401 10uF R405 28.7k U402 TPS74801DRC 10 OUT IN 9 IN OUT 8 FB PG 7 BIAS D.N.C 6 GND EN 11 SW_1.05V C412 1000pF 2.2uH L402 + C408 J406 J408 EN_1.
SLUU465 – November 2010 Submit Documentation Feedback © 2010, Texas Instruments Incorporated R513 100k R511 8.06k R503 10.0k R502 5.62k R501 68.1 C508 0.01uF C501 1uF D501 BAT54 R512 10.0k C509 1uF EN_1.2V TP504 PG_1.2V TP503 C502 0.01uF GND TP502 17 16 15 14 13 R504 100k An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System 28 R508 10.0k R507 10.0k 9 12 11 10 J501 TP505 1 R506 1 C506 SW_1.2V SW501 OFF ON U504A:A SN74HC08D SW502 GPUDyn Load OFF CPUDyn.
Test Setup www.ti.com 5 Test Setup 5.1 Test Equipment Voltage Source VIN: The input voltage source VIN must be a 0-V to 14-V variable dc source capable of supplying 10 Adc. Connect VIN to J304 as shown in Figure 7. Multimeters: V1: Vin at TP303 (VIN) and TP304 (GND) V2: Vout at each output test point. For example: CPU at J101 A1: Vin input current Output Load: The output load must be an electronic constant resistance mode load capable of 0 Adc to 10 Adc.
Configuration www.ti.com Input Connections: 1. Prior to connecting the dc input source VIN, it is advisable to limit the source current from VIN to 10 A maximum. Ensure that VIN is initially set to 0 V and connected as shown in Figure 7. 2. Connect a voltmeter V1 at TP303 (VIN) and TP304 (GND) to measure VIN input voltage. 3. Connect a current meter A1 between VIN dc source and J304. Output Connections (For example, CPU testing) 1.
Configuration 6.1.4 www.ti.com VID Bits Selection The CPU Vcore voltage can be set by J107( 7-Bit CPU VID). Default setting: 0101000 for 1.000V Jumper = 1 No Jumper = 0 Table 5. CPU VID Bits Selection 7-Bit VID Table (1 = 1.05 V, 0 = GND) VID6 VID5 VID4 VID3 VID2 VID1 VID0 Vcore(V) 0 0 0 0 0 0 0 1.500 0 0 1 1 0 0 0 1.200 0 1 0 1 0 0 0 1.000 0 1 1 1 0 0 0 0.800 1 0 0 1 0 0 0 0.600 1 0 1 1 0 0 0 0.400 1 1 0 0 0 0 0 0.
Configuration www.ti.com Table 8. Overvoltage Protection selection Jumper set to 6.1.7 Selection No jumper OVP enabled Jumper shorted OVP disabled Onboard Dynamic Load Selection (SW501 for CPU and SW502 for GPU) The onboard dynamic load can be set by SW501 and SW502. Default setting: Push SW501 and SW502 to the right to disable the onboard dynamic load. Table 9. Onboard Dynamic Load Selection 6.1.
Configuration www.ti.com Note: 1.05V enable is for VID setting of CPU and GPU Table 12. 1.8-V/1.05-V Enable Selection 6.4 6.4.1 Jumper set to Selection Jumper on J402 1.8V Disabled No Jumper on J402 1.8V Enabled Jumper on J401 1.05V Disabled No Jumper on J401 1.05V Enabled 0.9-V VTT and 0.9-V VTTREF Configuration 0.9-V VTT and 0.9-V VTTREF Enable Selection (SW401 for S3, SW400 for S5) Default setting: Push SW400 and SW401 to bottom to disable both 0.9VTT and 0.9VTTREF. Table 13.
Test Procedure www.ti.com 6.7 6.7.1 1.2-V IOH Configuration 1.2-V Enable Selection (J501) 1.2-V Enable can be set by J501, EN_1.2V Default setting: Jumper shorts on J501 to disable 1.2 V Table 16. 1.2-V Enable selection Jumper set to Selection No Jumper 1.2V Enabled Jumper on 1.2V Disabled 7 Test Procedure 7.1 Line/Load Regulation and Efficiency Measurement Procedure The CPU measurement is performed in the following manner. 1. Set up EVM as described in Section 5.1 and Figure 7. 2.
Test Procedure 7.3 www.ti.com Loop Gain/Phase Measurement CPU and GPU Only 1. Set up EVM as described in Section 5.1 and Figure 7. 2. CPU: Connect the isolation transformer to VSNS of J101 (CPU) and Vcore_C (+)(CPU) of J102. GPU: Connect the isolation transformer to VSNS of J201 (GPU) and Vcore_G (+)(GPU) of J202 3. CPU: Connect input signal CHA to VSNS pin of J101 and connect output signal CHB to Vcore_C(+) of J102.
Performance Data and Typical Characteristic Curves www.ti.com 8 Performance Data and Typical Characteristic Curves Figure 8 through Figure 68 present typical performance curves for TPS59610EVM-634. Jumpers set to default locations; see Section 6 of this user’s guide 8.1 CPU 100 1.04 VI = 12 V 90 VI = 8 V 1.02 VO - Output Voltage - V 80 Efficiency - % 70 VI = 14 V 60 50 40 30 VI = 12 V VI = 8 V SPEC_nom SPEC_max 1 0.98 VI = 14 V 0.96 20 SPEC_min 10 0.94 0 0.001 0.01 0.
Performance Data and Typical Characteristic Curves TPS9610EVM-634 CPU Switching Node www.ti.com TPS9610EVM-634 CPU Output Ripple Test Condition: 12 Vin, 1 V/5 A Test Condition: 12 Vin, 1 V/5 A CH1: LL_C CH1: 1 Vcore Output Ripple Figure 13. CPU Vcore Ripple Figure 12.
Performance Data and Typical Characteristic Curves www.ti.com TPS9610EVM-634 CPU Output Transient TPS9610EVM-634 CPU Output Transient Test Condition: 12 Vin, 1 V/0.04 A-5 A Transient CH1: 1 V core Output Test Condition: 12 Vin, 1 V/0.04 A-5 A Transient CH1: 1 V core Output CH3: LL CH3: LL CH4: 1 Vcore Output Current CH4: 1 Vcore Output Current Figure 16. CPU Transient From DCM to CCM Figure 17. CPU Transient From CCM to DCM Figure 18.
Performance Data and Typical Characteristic Curves www.ti.com TPS59610 Figure 19. CPU Top Board Figure 20.
Performance Data and Typical Characteristic Curves www.ti.com 8.2 GPU 100 90 VI = 12 V VI = 8 V 1.04 80 Efficiency - % VO - Output Voltage - V SPEC_max 70 VI = 14 V 60 50 40 30 1.02 VI = 14 V VI = 8 V 1 SPEC_nom 20 SPEC_min VI = 12 V 10 0 0.001 0.01 0.1 1 IO - Output Current - A 10 0.98 0 0.5 1 1.5 2 2.5 3 3.5 IO - Output Current - A 4 4.5 5 NOTE: Intel spec calls for 3% offset at the VID setting Figure 21. CPU Efficiency Figure 22.
Performance Data and Typical Characteristic Curves TPS9610EVM-634 GPU Switching Node www.ti.com TPS9610EVM-634 GPU Output Ripple Test Condition: 12 Vin, 1 V/5 A Test Condition: 12 Vin, 1 V/5 A CH1: LL_G 1 Vcore Output Ripple Figure 25. GPU Switching Node TPS9610EVM-634 GPU Over Shoot Reduction (OSR) Test Condition: 12 Vin, 1 V/5 A-0A Load Release Figure 26.
Performance Data and Typical Characteristic Curves www.ti.com TPS9610EVM-634 GPU Output Transient: OSR max TPS9610EVM-634 GPU Output Transient Test Condition: 12 Vin, 1 V/0 A-5 A Transient Test Condition: 12 Vin, 1 V/0 A-5 A Transient CH1: 1 Vcore CH2: 1 Vcore CH3: LL CH3: LL CH4: 1 Vcore Output Current CH4: 1 Vcore Output Current Figure 29. GPU Transient From DCM to CCM Figure 30. GPU Transient From CCM to DCM Figure 31.
Performance Data and Typical Characteristic Curves www.ti.com CSD86330Q3 TPS59610 Figure 33. CPU Bottom Board Figure 32. CPU Top Board Test condition: 12 Vin, 1 V/5 A, no airflow 8.3 5-V/3.3-V System 5.6 100 VI = 8 V 90 80 VI = 12 V 5.4 VI = 14 V VO - Output Voltage - V Efficiency - % 70 60 50 40 30 20 5.2 VI = 12 V VI = 14 V 5 VI = 8 V 4.8 4.6 10 0 0.001 0.01 0.1 1 IO - Output Current - A 10 Figure 34. 5-V Efficiency 26 4.4 0 1 2 3 IO - Output Current - A 4 5 Figure 35.
Performance Data and Typical Characteristic Curves www.ti.com TPS9610EVM-634 5 V Enable Start Up Test Condition: 12 Vin, 5 V/5 A TPS9610EVM-634 5 V Enable Shut Down Test Condition: 12 Vin, 5 V/5 A CH1: EN_5 V CH1: EN_5 V CH2: 5 Vout CH2: 5 Vout CH3: PG_5 V CH3: PG_5 V Figure 36. 5-V Enable Turnon TPS9610EVM-634 5 V Switching Node Figure 37.
Performance Data and Typical Characteristic Curves www.ti.com 3.35 100 VI = 8 V 90 80 VI = 12 V VO - Output Voltage - V Efficiency - % 70 VI = 14 V 60 50 40 30 VI = 14 V VI = 12 V 3.3 VI = 8 V 3.25 20 10 0 0.001 0.01 0.1 1 IO - Output Current - A 10 Figure 40. 3.3-V Efficiency TPS9610EVM-634 3.3 V Enable Start Up Test Condition: 12 Vin, 3.3 V/5 A 3.2 0 1 2 3 IO - Output Current - A 4 5 Figure 41. 3.3-V Load Regulation TPS9610EVM-634 3.
Performance Data and Typical Characteristic Curves www.ti.com TPS9610EVM-634 3.3 V Switching Node TPS9610EVM-634 3.3 V Output Ripple Test Condition: 12 Vin, 3.3 V/5 A Test Condition: 12 Vin, 3.3 V/5 A CH1: 3.3 V Output Ripple CH1: SW_3.3 V Figure 45. 3.3-V Vo Ripple Figure 44. 3.3-V Switching Node TPS51120 Figure 46. 5-V/3.3-V TOP Board Figure 47. 5-V/3.3-V Bottom Board Test condition: 12 Vin, 5 V/5 A and 3.
Performance Data and Typical Characteristic Curves 8.4 www.ti.com 1.8-V DDR/1.05-V CPU VTT 100 1.95 VI = 12 V VI = 8 V 90 1.9 80 VI = 14 V VO - Output Voltage - V Efficiency - % 70 60 50 40 30 20 VI = 12 V 1.85 VI = 14 V 1.8 VI = 8 V 1.75 1.7 10 0 0.001 1.65 0.01 0.1 1 IO - Output Current - A 10 Figure 48. 1.8-V Efficiency TPS9610EVM-634 1.8 V Enable Start Up 0 1 2 3 IO - Output Current - A 4 5 Figure 49. 1.8-V Load Regulation Test Condition: 12 Vin, 1.8 V/5 A TPS9610EVM-634 1.
Performance Data and Typical Characteristic Curves www.ti.com TPS9610EVM-634 1.8 V Switching Node TPS9610EVM-634 1.8 V Output Ripple Test Condition: 12 Vin, 1.8 V/5 A Test Condition: 12 Vin, 1.8 V/5 A CH1: 1.8 V Output Ripple CH1: SW_1.8 V Figure 52. 1.8-V Switching Node Figure 53. 1.8-V Vo Ripple 1.1 100 90 VI = 12 V VI = 8 V 80 VO - Output Voltage - V 1.08 Efficiency - % 70 VI = 14 V 60 50 40 30 20 VI = 14 V 1.06 VI = 12 V VI = 8 V 1.04 1.02 10 0 0.001 1 0.01 0.
Performance Data and Typical Characteristic Curves TPS9610EVM-634 1.05 V Enable Start Up TestCondition: Condition:12 12Vin, Vin,1.05 1.05V/5 V/5AA Test www.ti.com TPS9610EVM-634 1.05 V Enable Shut Down Test Condition: 12 Vin, 1.05 V/5 A CH1: EN_1.05 V CH1: EN_1.05 V CH2: 1.05 Vout CH2: 1.05 Vout CH3: PG_1.05 V CH3: PG_1.05 V Figure 56. 1.05-V Enable Turnon TPS9610EVM-634 1.05 V Switching Node Test Condition: 12 Vin, 1.05 V/5 A Figure 57. 1.05-V Enable Turnoff TPS9610EVM-634 1.
Performance Data and Typical Characteristic Curves www.ti.com TPS59124 CSD86330Q3D Figure 60. 1.8-V/1.05-V Top Board Figure 61. 1.8-V/1.05-V Bottom Board Test condition: 12 Vin, 1.8 V/5 A and 1.05 V/5 A, no airflow 8.5 1.2-V IOH 1.3 100 90 VI = 8 V VI = 12 V 1.28 80 VO - Output Voltage - V 1.26 Efficiency - % 70 VI = 14 V 60 50 40 30 1.24 VI = 14 V 1.22 1.2 VI = 8 V 1.18 1.16 20 1.14 10 1.12 0 0.001 VI = 12 V 1.1 0.01 0.1 1 IO - Output Current - A Figure 62. 1.
Performance Data and Typical Characteristic Curves TPS9610EVM-634 1.2 V IOH Core Enable Start Up www.ti.com Test Condition: 12 Vin, 1.2 V/3 A TPS9610EVM-634 1.2 IOH Core Enable Shut Down CH1: EN_1.2 V CH1: EN_1.2 V CH2: 1.2 Vout CH2: 1.2 Vout CH3: PG_1.2 V CH3: PG_1.2 V Figure 64. 1.2-V Enable Turnon TPS9610EVM-634 1.2 V Switching Node Test Condition: 12 Vin, 1.2 V/3 A Test Condition: 12 Vin, 1.2 V/3 A Figure 65. 1.2-V Enable Turnoff TPS9610EVM-634 1.2 V IOH Output Ripple CH1: 1.
EVM Assembly Drawings and PCB Layout www.ti.com 9 EVM Assembly Drawings and PCB Layout The following figures (Figure 69 through Figure 74) show the design of the TPS59610EVM-634 printed circuit board. The EVM has been designed using 4 Layers circuit board with 2oz copper on outside layers. Figure 69. TPS59610EVM-634 Top Layer Assembly Drawing, Top View Figure 70. TPS59610EVM-634 Bottom Assembly Drawing, Bottom View Figure 71.
EVM Assembly Drawings and PCB Layout www.ti.com ` Figure 72. TPS59610EVM-634 Internal Layer 2, Top View Figure 73. TPS59610EVM-634 Internal Layer 3, Top View Figure 74.
Bill of Materials www.ti.com 10 Bill of Materials Table 17 shows the EVM major components list according to the schematic shown in Figure 2 through Figure 6. Table 17.
Bill of Materials www.ti.com Table 17. Bill of Materials (continued) Qty RefDes Description MFR Part Number 2 R106, R206 Resistor, Chip, 6.19k, 1/16W, 1%, 0603 STD STD 3 R109, R209, R305 Resistor, Chip, 0, 1/16W, 5%, 0402 STD STD 2 R110, R210 Resistor, Chip, 2.00k, 1/16W, 1%, 0603 STD STD 2 R111, R211 Resistor, Chip, 5.90, 1/16W, 1%, 0603 STD STD 2 R402, R409 Resistor, Chip, 0, 1/16W, 1%, 0603 STD STD 2 R112, R212 Resistor, Metal Film, 0.
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