Datasheet
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
VID0 1 Voltage identification input 0. The VID pins are tri-level programming pins that set the output voltages for both
converters. The code pattern for setting the output voltage is located in table 1. The VID pins are internally pulled to
V
BIAS
/2, allowing floating voltage set to logic 1 (see Table 1).
VID1 2 Voltage identification input 1 (see VID0 pin description and Table 1).
SLOWST 3 Slow-start (soft start). A capacitor from pin 3 to GND sets the slow-start time for V
OUT-RR
and V
OUT-LDO
. Both supplies
will ramp-up together while tracking the slow-start voltage.
VHYST 4 Hysteresis set pin. The hysteresis equals 2 × (VREFB − VHYST).
VREFB 5 Buffered ripple regulator reference voltage from VID network.
VSEN-RR 6 Ripple regulator voltage sense input. This pin is connected to the ripple regulator output. It is used to sense the ripple
regulator voltage for regulation, OVP, UVP, and power good functions. It is recommended that an RC low pass filter be
connected at this pin to filter high frequency noise.
ANAGND 7 Analog ground
BIAS 8 Analog BIAS pin. Recommended that a 1-µF capacitor be connected to ANAGND.
VLDODRV 9 Output of charge pump generated through bootstrap diode. Approximately equal to VDRV + V
IN
– 300 mV. Used as
supply for LDO driver and bias regulator. Recommended that a 1-µF capacitor be connected to DRVGND.
CPC1 10 Connect one end of charge pump capacitor. Recommended that a 1-µF capacitor be connected from CPC1 to CPC2.
V
CC
11 3.3 V or 5 V supply (2.8 V – 5.5 V). It is recommended that a low ESR capacitor be connected directly from V
CC
to
DRVGND (bulk capacitors supplied at power stage input).
CPC2 12 Other end of charge pump capacitor from CPC1.
VDRV 13 Regulated output of internal charge pump. Supplies DRIVE charge for the low-side MOSFET driver (5 V).
Recommended that a 10-µF capacitor be connected to DRVGND.
DRVGND 14 Drive ground. Ground for FET drivers. Connect to source of low-side FET.
LOWDR 15 Low drive. Output drive to synchronous rectifier low-side FET.
BOOTLO 16 Bootstrap low. This pin connects to the junction of the high-side and low-side FETs.
BOOT 17 Bootstrap pin. Connect a 1-µF low ESR capacitor to BOOTLO to generate floating drive for the high-side FET driver.
HIGHDR 18 High drive. Output drive to high-side power switching FETs
LOSENSE/
LOHIB
19 Low sense/low-side inhibit. This pin is connected to the junction of the high and low-side FETs and is used in current
sensing and the anti-cross-conduction to eliminate shoot-through current.
HISENSE 20 High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs.
IOUTLO 21 Current sense low output. Voltage on this pin is the voltage on the LOSENSE pin when the high-side FETs are on.
INHIBIT 22 This pin inhibits the drive signals to the MOSFET drivers. The IC is in a low-current state if INHIBIT is grounded. It is
recommended that an external pullup resistor be connected to 5 V.
NGATE-LDO 23 Drives external N-channel power MOSFET to regulate LDO voltage to VREF-LDO.
VSEN−LDO 24 LDO voltage sense. This pin is connected to the LDO output. It is used to sense the LDO voltage for regulation, OVP,
UVP, and power good functions.
PWRGD 25 Power good. Power good signal goes high when output voltage is above 93% of V
REF
for both ripple regulator and
LDO. This is an open-drain output.
IOUT 26 Current signal output. Output voltage on this pin is proportional to the load current as measured across the high-side
FETs on-resistance. The voltage on this pin equals 2 × R
ON
× IOUT, where R
ON
is the equivalent on-resistance of the
high-side FETs
OCP 27 Over current protection. Current limit trip point for ripple regulator is set with a resistor divider between the IOUT pin and
ANAGND. The trip point is typically 125 mV.
DROOP 28 Droop voltage. Voltage input used to set the amount of output voltage droop as a function of load current. The amount of
droop compensation is set with a resistor divider between the IOUT pin and ANAGND.