Datasheet


 
     
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
CC
23
24
VLDODRV
NGATE−LDO
VSEN−LDO
RR_OVP
LDO_OVP
RR_UVP *
LDO_UVP *
SHUTDOWN
VID
2
1
VID0
VID1
VREF_LDO
VREF_RR
5
VREFB
Hysteresis
Setting
+
−
28
VHYST
6
VSEN−RR
Hysteresis
Comparator
Adaptive
Deadtime
15
18
16
14
17
VDRV
BOOT
HIGHDR
BOOTLO
LOWDR
DRVGND
22
11
INHIBIT
V
VDRV UVLO
V
3
SLOWST
SHUTDOWN
+
−
−
+
Delay
26202119
LOSENSE/
LOHIB
IOUTLO HISENSE
IOUT
HIGHDR
Ivrefb/5
Vbias
8
Bias
7
Reg.
VLDODRV
25
>0.93xVSEN−RR
>0.93xVSEN−LDO
4
DROOP
PWRGD
ANAGND
SHUTDOWN
27
125 mV
OCP
RS
Q
Fault
Latch
SHUTDOWN
INHIBIT
SLOWST
SLOWST
SHUTDOWN
SHUTDOWN
5 V
10
CPC1
9
12
CPC2
13
VDRV
VDRV
BOOT
−
+
E/A
Synchronous
FET
RR−Ripple Regulator
(see Table 1)
VDRV
* UVP is disabled during slowstart
CC
UVLO