Datasheet
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout and component value consideration (continued)
5. When configuring the high-side driver as a boot-strap driver, the connection from BOOTLO to the power
FETs should be as short and as wide as possible. LOSENSE/LOHIB should have a separate connection
to the FETs since BOOTLO will have large peak current flowing through it.
6. The bulk storage capacitors across V
IN
should be placed close to the power FETs. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
7. HISENSE and LOSENSE/LOHIB should be connected very close to the drain and source, respectively, of
the high-side FET. HISENSE and LOSENSE/LOHIB should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to V
IN
, to reduce high-frequency noise coupling on HISENSE.
The EVM board (SLVP-139) is used in the test. The test results are shown in the following.
Figure 23
I
O
− Output Current − A
EFFICIENCY OF
RIPPLE REGULATOR (3.3 V)
60
40
13
80
70
50
245
100
0
Efficiency − %
90
V
IN
= 5 V
Figure 24
I
O
− Output Current − A
RIPPLE REGULATOR
LOAD REGULATION (3.3 V)
−2
13
0
−1
245
1
0
2
V
IN
= 5 V
Load Regulation − %