Datasheet
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
To promote better system reliability during power up, voltage sequencing and protection are controlled such that
the core and I/O power up together with the same slow-start voltage. At power down, the LDO and ripple
regulator are discharged towards ground for added protection. The TPS56302 also includes inhibit, slow-start,
and under-voltage lockout features to aide in controlling power sequencing. A tri-level voltage identification
definition (VID) sets both regulated voltages to any of 9 preset voltage pairs from 1.3 V to 3.3 V. Other voltages
are possible by implementing an external voltage divider. Strong MOSFET drivers, with a typical peak current
rating of 2-A sink and source are included on chip, which allows paralleling MOSFETs to be driven and allowing
higher current to be controlled. The high-side driver features a floating bootstrap driver with an internal bootstrap
synchronous rectifier. Many protection features are incorporated within the device to ensure better system
integrity. An open-drain output power good status circuit monitors both output voltages, and is pulled low if either
output falls below the threshold. An over current shutdown circuit protects the high-side power MOSFET against
short-to-ground faults, while over voltage protection turns off the output drivers and LDO controller if either
output exceeds its threshold. Under voltage protection turns off the high-side and low-side MOSFET drivers and
the LDO controller if either output is 25% below V
REF
. Lossless current-sensing is implemented by detecting
the drain-source voltage drop across the high-side power MOSFET while it is conducting. The TPS56302 is fully
compliant with TI DSP power requirements.
AVAILABLE OPTIONS
PACKAGES
T
J
TSSOP
†
(PWP)
EVALUATION MODULE
−40°C to 125°C TPS56302PWP TPS56302EVM−163 (SLVP163)
†
The PWP package is also available taped and reel. To order, add an R to the end of
the part number (e.g., TPS56302PWPR).
Table 1. Voltage Identification Code
¶#
VID TERMINALS
‡
56302 56300
VID1 VID0
V
REF−LDO
#
(VDC)
V
REF−RR
#
(VDC)
V
REF−RR
#
(VDC)
V
REF−LDO
#
(VDC)
0 0 1.30 1.50 1.30 1.50
0 1 1.50 1.80 1.50 1.80
0 2 1.30 1.80 1.30 1.80
1 0 1.80 3.30 1.80 3.30
1 1 1.30 1.30 1.30 1.30
1 2 2.50 3.30 2.50 3.30
2 0 1.30 2.50 1.30 2.50
2 1 1.50 3.30 1.50 3.30
2 2 1.80 2.50 1.80 2.50
‡
0 = ground (GND), 1 = floating(V
BIAS
/2), 2 = (V
BIAS
)
§
RR = Ripple Regulator, LDO = Low Drop-Out Regulator
¶
V
BIAS
/2 is internal, leave the VID pin floating. Adding an external 0.1-µF capacitor to ANAGND may be used
to avoid erroneous level.
#
External resistors may be used as a voltage divider (from V
OUT
to VSEN−xx to ground) to program output
voltages to other values.