Datasheet

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SLVS289A − MARCH 2000 − REVISED OCTOBER 2000
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
V
CC
and VDRV undervoltage lockout
The V
CC
undervoltage lockout circuit disables the controller while the V
CC
supply is below the 2.8-V start
threshold. The VDRV undervoltage lockout circuit disables the controller while the VDRV supply is below the
4.9 V start threshold during powerup. While the controller is disabled, the output drivers will be low, the LDO
drive is off, and the slow-start capacitor will be shorted. When V
CC
and VDRV exceed the start threshold, the
short across the slow-start capacitor is released and normal converter operation begins. Recycling V
CC
or
toggling the INHIBIT pin from low to high clears the fault latch.
power good
The power good circuit monitors for an undervoltage condition on V
OUT−RR
and V
OUT−LDO
. The power good
(PWRGD) pin is pulled low if either V
OUT−RR
is 7% below V
REF−RR
, or V
OUT−LDO
is 7% below V
REF−LDO
.
PWRGD is an open drain output. The PWRGD pin is also pulled down, if either V
CC
or VDRV are below their
UVLO thresholds.
overvoltage protection
The overvoltage protection circuit monitors V
OUT−RR
and V
OUT−LDO
for an overvoltage condition. If V
OUT−RR
or V
OUT−LDO
are 15% above their reference voltage, then a fault latch is set and both output drivers and LDO
are turned off. The latch remains set until the V
CC
or inhibit voltages go below their undervoltage lockout turnoff
values. A 1-µs to 5 µs deglitch timer is included for noise immunity.
overcurrent protection
The overcurrent protection circuit monitors the current through the high-side FET. The overcurrent threshold
is adjustable with an external resistor divider between IOUT and ANAGND pins, with the divider voltage
connected to the OCP pin. If the voltage on the OCP pin exceeds 125 mV, a fault latch is then set and the output
drivers are turned off. The latch remains set until the V
CC
or inhibit voltages go below their undervoltage lockout
values. A 1-µs to 5-µs deglitch timer is included for noise immunity. The OCP circuit is also designed to protect
the high-side power FET against a short-to-ground fault on the terminal common to both power FETs.
undervoltage protection
The undervoltage protection circuit monitors V
OUT−RR
and V
OUT−LDO
for an undervoltage condition. If V
OUT−RR
or V
OUT−LDO
is 15% below their reference voltage, then a fault latch is set and both output drivers and LDO are
turned off. The latch remains set until the V
CC
or inhibit voltages go below their undervoltage lockout values.
A 100-µs to 1-ms deglitch timer is included for noise immunity.
synchronous charge pump
The regulated synchronous charge pump provides drive voltage to the low-side driver at VDRV (5 V), and to
the high-side driver configured as a floating driver. The minimum drive voltage is 4.5 V, (typical is 5 V). The
minimum short-circuit current is 80 mA. The bootstrap capacitor is used to provide voltage for the high-side FET,
the power for VLDODRV, and the bias regulator. Instead of diodes, synchronous rectified MOSFETs are used
to reduce voltage drop losses and allow a lower input voltage threshold. The charge pump oscillator operates
at 300 kHz until the UVLO VDRV is set; after which it is synchronized to the converter switching frequency and
is turned on and off to regulate VDRV at 5 V.
The charge pump is designed to operate at a switching frequency of 200 kHz to 400 kHz. Operation at low
frequency may require larger capacitors on the CPCx and VDRV pins. Higher frequencies (> 400 kHz) may not
be possible.
power sequence
The V
OUT−LDO
voltage is powered up with respect to the same slow-start reference voltage as the V
OUT−RR
Also, at power down, the V
OUT−RR
and V
OUT−LDO
are discharged to ground through P-channel MOSFETs in
series with 1-kΩ resistors.