SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 D 2.8 V – 5.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 description (continued) To promote better system reliability during power up, voltage sequencing and protection are controlled such that the core and I/O power up together with the same slow-start voltage. At power down, the LDO and ripple regulator are discharged towards ground for added protection.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 functional block diagram LOSENSE/ LOHIB PWRGD 25 Bias IOUTLO 19 HISENSE IOUT 20 26 21 + 8 − >0.93xVSEN−RR Reg. VDRV VLDODRV >0.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 Terminal Functions TERMINAL NAME DESCRIPTION NO. VID0 1 VID1 2 SLOWST 3 Slow-start (soft start). A capacitor from pin 3 to GND sets the slow-start time for VOUT-RR and VOUT-LDO. Both supplies will ramp-up together while tracking the slow-start voltage. VHYST 4 Hysteresis set pin. The hysteresis equals 2 × (VREFB − VHYST).
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)† Supply voltage range, VCC (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Input voltage range: VDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) input PARAMETER VCC ICC TEST CONDITIONS MIN Supply voltage range TYP MAX 2.8 Quiescent current INHIBIT = 0 V, 5.5 VCC = 5 V 15 UNITS V mA NOTE 2: Ensured by design, not production tested.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued) slow-start PARAMETER CONDITIONS Charge current V(S/S) = 0.5 V, Resistance from VREFB pin to ANAGND = 20 kΩ VREFB = 1.3 V, Ichg = (IVREFB/5) Discharge current V(S/S) = 1.3 V MIN TYP MAX UNITS 10.4 13 15.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued) high-side VDS sensing PARAMETER CONDITIONS MIN Gain Initial accuracy Common-mode rejection ratio Sink current (IOUTLO) TYP MAX 2 VHISENSE = 3.3 V, VIOUTLO = 3.2 V, Differential input to Vds sensing amp = 100 mV VHISENSE=2.8 V to 5.5 V, VHISENSE− VIOUTLO=100 mV 2.8 V < VIOUTLO < 5.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued) thermal shutdown PARAMETER CONDITIONS MIN TYP MAX UNITS See Note 2 145 °C Hysteresis See Note 2 NOTE 2. Ensured by design, not production tested. 10 °C Over temperature trip point synch charge pump regulator PARAMETER Internal oscillator frequency CONDITIONS 2.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued) output drivers (see Note 5) PARAMETER Peak output current MIN TYP Duty cycle < 2%, tpw < 100 us, VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 4 V (sink), See Note 2 and Figure 15 CONDITIONS 0.7 2 Duty cycle < 2%, tpw < 100 us, VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 0.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued) VSENSE−RR and VSENSE−LDO discharge PARAMETER CONDITIONS VSENSE−RR discharge FET current saturation VSENSE−RR discharge series resistance (limits current) VSENSE−RR = 1.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 detailed description (continued) deadtime control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turnon time of the MOSFET drivers.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 detailed description (continued) VCC and VDRV undervoltage lockout The VCC undervoltage lockout circuit disables the controller while the VCC supply is below the 2.8-V start threshold. The VDRV undervoltage lockout circuit disables the controller while the VDRV supply is below the 4.9 V start threshold during powerup.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs JUNCTION TEMPERATURE VCC UVLO HYSTERESIS vs JUNCTION TEMPERATURE 180 13 VCC = 3.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS SLOW-START TIME vs SUPPLY CURRENT (VREFB) SLOW-START TIME† vs SLOW-START CAPACITANCE 1000 100 VCC = 3.3 V V(VREFB) = 1.3 V I(VREFB) = 65 µA TJ = 25°C Slowstart Time − ms Slowstart Time − ms VCC = 3.3 V V(VREFB) = 1.3 V CS = 0.1 µF TJ = 27°C 100 10 1 1 10 100 10 1 0.1 0.0001 1000 0.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 DRIVER DRIVER HIGH-SIDE OUTPUT RESISTANCE vs JUNCTION TEMPERATURE LOW-SIDE OUTPUT RESISTANCE vs JUNCTION TEMPERATURE 5.0 8 4.5 7 R O − Low-Side Output Resistance − Ω R O − High-Side Output Resistance − Ω TYPICAL CHARACTERISTICS 4.0 3.5 3.0 2.5 2.0 1.5 1.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS RIPPLE REGULATOR POWER GOOD THRESHOLD vs JUNCTION TEMPERATURE VDRV UVLO HYSTERESIS vs JUNCTION TEMPERATURE 96 Ripple Regulator Powergood Threshold − % 300 VDRV UVLO Hysteresis − mV 280 260 240 220 200 180 160 140 120 95 94 93 92 91 90 89 88 100 0 25 50 75 100 TJ − Junction Temperature − °C 0 125 Figure 13 INHIBIT HYSTERESIS VOLTAGE vs JUNCTION TEMPERATU
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS RIPPLE REGULATOR OVP THRESHOLD vs JUNCTION TEMPERATURE RIPPLE REGULATOR UVP THRESHOLD vs JUNCTION TEMPERATURE Ripple Regulator UVP Threshold − % 77 117 116 115 114 113 112 0 25 50 75 100 76 75 74 73 72 71 125 0 25 TJ − Junction Temperature − °C 50 75 100 125 TJ − Junction Temperature − °C Figure 17 Figure 18 OCP THRESHOLD VOLTAGE vs JU
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS LDO OVP THRESHOLD vs JUNCTION TEMPERATURE 118 LDO OVP Threshold − % 117 116 115 114 113 112 0 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 20 LDO UVP THRESHOLD vs JUNCTION TEMPERATURE 77 LDO UVP Threshold − % 76 75 74 73 72 71 0 25 50 75 100 TJ − Junction Temperature − °C Figure 21 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION evaluation module In many DSP applications, the voltage bus powering DSP I/O also has to power peripheral circuitry. The total current is much higher than the requirement for the I/O only. This is the reason to use the high-efficiency ripple regulator to power I/O. In turn, the core power is delivered by LDO output.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION Table 3. Ripple Regulator Power Stage Components Ref Des Function 4A (EVM Design) Ripple Regulator Section 8A† 12A† 20A† C3, C6 Input bulk capacitor C3: open C6: 150 µF (Sanyo, 6TPB150M) C3: 150 µF C6: 150 µF (Sanyo, 6TPB150M) C3: 150 µF C6: 150 µF (Sanyo, 6TPB150M) C3: 150 µF C6: 2x150 µF (Sanyo, 6TPB150M) C11, C2 Input high-freq capacitor C2: 0.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION Table 4. LDO Power Stage Components LDO Section Ref.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION hysteresis window The changeable hysteresis window in TPS56302 is used for switching frequency and output voltage ripple adjustment. The hysteresis window setup is decided by a two-resistor voltage divider on VREFB and VHYST pin. Two times the voltage drop on the top resistor is the hysteresis window.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION droop compensation Droop compensation with the offset resistor divider from VOUT to the VSENSE is used to keep the output voltage in range during load transients by increasing the output voltage setpoint toward the upper tolerance limit during light loads and decreasing the voltage setpoint toward the lower tolerance limit during heavy loads.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION output capacitor RMS current Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the output capacitor can be calculated as: IO(rms) = ∆I 12 Where IO(rms) is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple current (A). Example: ∆I = 1 A, so IO(rms) = 0.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION layout and component value consideration (continued) 5. When configuring the high-side driver as a boot-strap driver, the connection from BOOTLO to the power FETs should be as short and as wide as possible. LOSENSE/LOHIB should have a separate connection to the FETs since BOOTLO will have large peak current flowing through it. 6.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION RIPPLE REGULATOR LINE REGULATION (3.3 V) LDO LOAD REGULATION (1.8 V) 2 2 VIN = 5 V 1 1 Line Regulation − % Line Regulation − % IO = 2 A 0 −1 0 −1 −2 3.5 3 4.5 4 5.5 5 −2 6 0 0.2 VIN − Input Voltage − V 0.4 Figure 25 5 5 VO − Output Voltage − V I L − Load Current − A VO − Output Voltage − mV 6 0 No Droop Output Voltage 200 100 1.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION layouts 3 in 2.7 in Figure 29. Top Layer Figure 30.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION bill of materials REF PN Description MFG Size C1 10TPA33M Capacitor, POSCAP, 33 µF, 10 V Sanyo C C2, C20, C21, C30, C31 Std Capacitor, Ceramic, 10 µF, 16 V Sanyo 1210 C3. C6, C8, C13, C25 6TPB150M Capacitor, POSCAP, 150 µF, 6 V Sanyo D C4, C5, C11, C12, C23, C26, C27, Std Capacitor, Ceramic, 0.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION Power Supply 5−V, 5−A Supply − + Load + 0−4A − 6.8 Ohms 2W Jumper Pins 2−3 NOTE A: All wire pairs should be twisted. Figure 31.
SLVS289A − MARCH 2000 − REVISED OCTOBER 2000 APPLICATION INFORMATION DSP power application In DSP power applications, TPS56302 is used in the applications that require more current for peripheral and DSP I/O. The power good (PG) output can be used for monitoring or controlling as an optional function. In the EVM schematic, Q3, D1, R1, and R2 are the circuit to show this function.
PACKAGE OPTION ADDENDUM www.ti.com 3-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS56302PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS56302PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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