Datasheet

TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout considerations (continued)
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5602.
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
The bulk storage capacitors across V
IN
should be placed close to the power FETs. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
High-frequency bypass capacitors should be placed across the bulk storage capacitors on V
O
.
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic decoupling capacitors should be placed close to where HISENSE connects to V
IN
, to
reduce high-frequency noise coupling on HISENSE.
The output voltage sensing trace should be isolated from the switching node and/or inductor pulses by the
use of a ground trace or plane.
test results
The tests are conducted at T
A
= 25°C, the input voltage is 5 V (if not specifically noted).
Figure 14
3.3-V OUTPUT EFFICIENCY
76
78
80
82
84
86
88
90
92
94
96
98
0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
I
O
– Output Current – A
Efficiency – %
Figure 15
1.8-V OUTPUT EFFICIENCY
60
65
70
75
80
85
90
95
0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
I
O
– Output Current – A
Efficiency – %