Datasheet

TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
application for DSP power (continued)
sequencing and under voltage protection
The EVM design uses the standby pins to implement power sequencing. There are two ways to achieve the
protection: one uses a voltage supervisory circuit such as the TI TPS3305-18, the other uses a low cost
comparator, such as the TI TLV1391. The standby pin for the second channel is pulled low by either the
supervisory circuit or the external protection comparator until the first channel output voltage is above the
start-up threshold voltage. With the protection hysteresis, during the power down, if the core voltage is lower
than, for example, 1.3 V, the 3.3 output will be pulled down together. During the normal operation, if the core
voltage is lost, the I/O voltage will be pulled down at the same time. This protection circuit prevents the DSPs
from any damage caused by the malfunctioning power supply. The equation displayed below uses the
comparator for the protection setpoint:
Assuming R16 is much larger than R17, and R19 is 10 kΩ, and the R13 value is adjusted for the turnon setpoint:
R13
(Von 1.2)
R16 R19
1.2
Where Von is the required turn on setpoint. For the turn-off setpoint, R16 is adjusted,
R16
R13 R19 (1.2 Vin)
R19 (Voff 1.2) 1.2 R13
By solving these equations together, or using a spreadsheet to iterate, the setpoints can be easily derived. The
two equations are used for the verification:
Von
1.2 (R13
R16 R19
R16 R19
and Voff R13
1.2 Vin
R16
1.2
R19
1.2
R13
Where Von and Voff are the turnon and turnoff setpoints respectively
Example can be found by using the numbers in the bill of materials.
layout considerations
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, placing the low-level components. Below are several specific points to
consider before layout of a TPS5602 design begins.
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on V
O
, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
The bypass capacitor for V
CC
should be placed close to the TPS5602.