Datasheet

( ) ( )
(
)
( )
( )
( )
2
2
2
CON1 OUT
DS on QSW RMS DS on
P R I R I D 0.085 3 A 0.540 0.562 W= ´ » ´ ´ = W ´ ´ =
(53)
( ) ( )
(
)
( )
( )
( )
2
2
2
CON2 OUT
DS on QSW RMS DS on
P R I R I D 0.085 3 A 0.370 0.465 W= ´ » ´ ´ = W ´ ´ =
(54)
( )
(
)
( )
2
2
Dj OSS SW
IN max
SW1 SW2
V (C C ) f
13.2 (200pF 250pF) 600kHz
P P 23.5mW
2 2
´ + ´
´ + ´
= » = =
(55)
( ) ( )
(
)
REG DD BP BP
IN max IN max
P I V I V V 5mA 13.2 V 66mW» ´ + ´ - = ´ =
(56)
DESIGN EXAMPLE 1 TEST RESULTS
0.15
75
70
1.15
85
80
90
100
95
h – Efficiency – %
0.65 1.65 2.652.15 3.15
14
8
12
V
IN
(V)
V
IN
= 14 V
V
IN
= 12 V
V
IN
= 8 V
I
LOAD
– Load Current – A
V
OUT
= 5 V
0.15 1.150.65 1.65 2.652.15 3.15
I
LOAD
– Load Current – A
75
70
85
80
90
100
95
h – Efficiency – %
14
8
12
V
IN
(V)
V
IN
= 14 V
V
IN
= 12 V
V
IN
= 8 V
V
OUT
= 3.3 V
TPS55383 , , TPS55386
www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008
Power Dissipation
The power dissipation in the TPS55386 is from FET conduction losses, switching losses and regulator losses.
Conduction losses are estimated by:
The switching losses are estimated by:
The regulator losses are estimated by:
Total power dissipation in the device is the sum of conduction and switching losses for both channels plus
regulator losses, and are estimated to total 1.2 W.
EFFICIENCY EFFICIENCY
vs vs
LOAD CURRENT LOAD CURRENT
Figure 34. Figure 35.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): TPS55383 TPS55386